Semiconductor memory device provided with capacitors formed above and below a cell transistor
AssigneeSamsung Electronics Co., Ltd.
InventorJoo-young Lee
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device provided with capacitors formed above and below a cell transistor includes first and second transistors formed in a first level, a first storage electrode connected to the first transistor and formed below the first level, and a second storage electrode connected to the second transistor and formed above the first level. The first and second storage electrodes are connected to each source via a spacer formed on the sidewalls of each source, and undercuts are formed between the storage electrode and the transistor, to thereby obtain double or more cell capacitance, a stable cell transistor characteristic and reduced short-channel effects.
Claims13
A semiconductor memory device having capacitors formed above and below a cell transistor, comprising:
- first and second transistors formed on a first level;
- a lower stacked storage electrode connected to said first transistor and formed below said first level;
- and
- an upper stacked storage electrode connected to said second transistor and formed above said first level.
A semiconductor memory device having capacitors formed above and below a cell transistor comprising:
- first and second transistors formed on a first level;
- a lower storage electrode connected to said first transistor and formed below said first level;
- and
- an upper storage electrode connected to said second transistor and formed above said first level, wherein said transistors each include a source having a side surface, and wherein a spacer formed on said side surface connects said storage electrodes respectively to said transistors.
A semiconductor device provided with capacitors formed above and below a cell transistor, comprising:
- first and second active regions separately formed;
- a first transistor whose source is formed in an edge portion of said first active region and a second transistor whose source is formed in an edge portion of said second active region;
- a first spacer formed on the sidewalls of the source of said first transistor and a second spacer formed on the sidewalls of the source of said second transistor;
- and
- a lower storage electrode connected to said first spacer and an upper storage electrode connected to said second spacer.
Dependencies are inferred from the claim text.