Pilot transistor for quasi-vertical DMOS device

An integrated circuit comprising:

• a semiconductor substrate with a first conductivity;
• an epitaxial layer of a second, opposite conductivity;
• a quasi-vertical DMOS (QVDMOS) transistor having:
• a highly conductive QVDMOS buried layer region of said second conductivity located at the interface between said semiconductor substrate and said epitaxial layer;
• an array of QVDMOS gates covering a portion of the surface of said epitaxial layer and electrically isolated from said epitaxial layer;
• an array of QVDMOS body regions of said first conductivity located in the surface of said epitaxial layer and extending under the edges of said QVDMOS gate array for defining QVDMOS channel regions of the QVDMOS transistor, said QVDMOS channel regions having in the aggregate a QVDMOS channel resistance;
• an array of QVDMOS drift regions in said epitaxial layer between said QVDMOS channel regions and said QVDMOS buried layer, said QVDMOS drift regions having in the aggregate a QVDMOS drift resistance;
• an array of QVDMOS source regions of said second conductivity located in the QVDMOS body regions and extending to some of the edges of said QVDMOS gate array and contacting said QVDMOS channel regions;
• highly conductive QVDMOS drain regions of said second conductivity extending from the surface of the epitaxial layer to the buried layer and separated from said arrays of QVDMOS gate and QVDMOS body regions;
• a QVDMOS buried layer resistance comprising the aggregate of distributed contributions to resistance in the QVDMOS current flow path from said QVDMOS buried layer below the QVDMOS drain regions and the QVDMOS buried layer below said QVDMOS drift regions;
• said QVDMOS transistor having a total resistance comprising the combined resistances of the QVDMOS channel, QVDMOS drift, and QVDMOS buried layer resistances;
• a pilot transistor electrically isolated from the QVDMOS transistor, said pilot transistor having:
• a pilot gate covering a portion of the surface of said epitaxial layer over a pilot buried layer and electrically isolated from said epitaxial layer;
• a pilot channel region disposed beneath the pilot gate region;
• a pilot body region of said first conductivity located in the surface of said epitaxial layer and extending under the edge of said pilot gate for defining a pilot channel region of the pilot transistor, said pilot channel region having a pilot channel resistance;
• a pilot source region of said second conductivity located in said pilot body region and extending to the edge of said pilot gate and contacting said pilot channel region;
• a highly conductive pilot buried layer region of second conductivity located at the interface between said semiconductor substrate and said epitaxial layer and having a pilot buried layer resistance;
• a pilot source drift region located in said epitaxial layer between said pilot channel region and said pilot buried layer and having a pilot source drift resistance;
• a pilot drain region spaced from the pilot gate and body regions, having a second conductivity;
• a pilot drain drift region located in said epitaxial layer between said buried layer and said pilot drain region and having a pilot drain drift resistance;
• a pilot drift resistance comprising the combination of said pilot source drift resistance and said pilot drain drift resistance;
• said pilot transistor having a total pilot resistance comprising the combination of said pilot channel, pilot drift and pilot buried layer resistances wherein each of said pilot channel, pilot drift and pilot buried layer resistances has the same relative ratio to the total pilot resistance as each of the corresponding QVDMOS channel, QVDMOS drift and QVDMOS buried layer resistances has to the total QVDMOS resistance.