Digital testing of analog memory devices

An integrated circuit comprising:

• an array of analog memory cells;
• means for writing in the array a value represented by an analog input signal;
• means for reading the array to generate an analog output signal representing a value read from the array;
• and
• digitally operable test circuitry comprising:
• means for using the writing means to write a test value to the array;
• and
• means for generating a digital output signal indicating whether the analog output signal from the reading means accurately represents the test value.

A method for testing an analog memory, comprising the steps of:

• providing resistor tree structure incorporated on-chip with the analog memory;
• writing to a selected memory cell in the analog memory a value represented by a first voltage from the resistor tree structure;
• reading the selected memory cell to generate an analog output signal representing a value read from the selected memory cell;
• comparing the analog output signal to a second voltage from the resistor tree structure;
• and
• generating a digital signal which indicates whether the analog output signal is at a voltage level greater than the second voltage.

An integrated circuit comprising:

• analog circuitry which generates an analog output signal from an analog input signal;
• a reference voltage generator coupled to the analog circuitry, the reference voltage generator generating a first intermediate voltage, a second intermediate voltage, and a third intermediate voltage, wherein during testing of the analog circuitry, the reference voltage generator provides to the analog circuitry the first intermediate voltage in place of the analog input signal;
• a first analog comparator coupled to the analog circuitry and the reference voltage generator, wherein during testing of the analog circuitry, the first analog comparator generates a first digital signal indicating whether the analog output signal from the analog circuitry is greater than the second intermediate voltage;
• a second analog comparator coupled to the analog circuitry and the reference voltage generator, wherein during testing of the analog circuitry, the second analog comparator generates a second digital signal indicating whether the analog output signal from the analog circuitry is less than the third intermediate voltage;
• and
• a gate coupled to generate a digital result signal which is a logical AND of the first and second digital signals.