US 5,682,112 AGranted

Phase locked loop control apparatus

AssigneeNEC Corporation

InventorMasaya Fukushima

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Abstract

The phase locked loop (PLL) control apparatus includes a selector which selects input signals, for an active system and a standby system having a clock signal and a frame pulse signal synchronized with the clock signal, by means of a line switching signal. The phase difference between the frame pulses before and after the line switching is output by a frame pulse phase comparator. On the other hand, accompanying the line switching, a frequency divided clock output from a frequency divider is branched in a PLL control circuit which carries out the phase matching of the clocks. The branched clock is converted to pseudo clocks with duty factors larger than and smaller than 50% by a duty factor controller. A clock selector which selects one out of the frequency divided clock and the pseudo clock in response to the phase difference of the frame pulses is installed between a clock phase comparator and a low-pass filter of the PLL control circuit. The provision of a time gate which is linked with the line switching signal, it is also possible to terminate the phase matching after the lapse of a specified period of time. Furthermore, it is also possible to carry out a quicker and smoother phase matching by detecting the control voltage and setting the duty factor in response to the condition of the phase difference.

Claims17

Dependent claims

A phase locked loop control apparatus comprising:

selector means for outputting input clock signal and frame pulse by switching among a plurality of input signals including a plurality of input frame pulses and a plurality of input clock signals;
a phase locked loop control circuit including a low-pass filter, an amplifier connected to an output of said low-pass filter, a voltage controlled oscillator connected to an output of said amplifier, a frequency divider which is connected to an output of said voltage controlled oscillator and outputs a frequency divided clock, and a clock phase-comparator which compares a phase of said frequency divided clock with a phase of said selected input clock signal provided from said selector means and outputs a reference clock having a duty factor that varies in response to a clock phase difference between said phase of said frequency divided clock and said phase of said selected input clock signal;
frame pulse phase comparison means for outputting a frame phase difference signal by comparing phases of said frequency divided clock and said selected frame pulse provided from said selector means;
frequency divided clock branching means for outputting branched frequency divided clocks by branching said frequency divided clock;
duty factor control means for receiving said branched frequency divided clocks and outputting pseudo clocks by setting duty factors of said branched frequency divided clock to predetermined values;
and
clock selection means arranged between said frame pulse phase comparison means and said low-pass filter for selecting one of said reference clock and said pseudo clocks in response to said frame phase difference signal.

4 more elements

A phase locked loop control apparatus comprising:

selection means for outputting a selected frame pulse and a selected clock by receiving first input signals and second input signals, said first input signals including a first input frame pulse and a first input clock, and said second input signals including a second input frame pulse and a second input clock, said first and second input clocks having a frequency f, said selection means switching lines of said first and second input signals in response to a line switching signal;
a low-pass filter which passes a low frequency part of a voltage of a phase control clock and outputs a low frequency voltage;
an amplifier which outputs a control voltage by amplifying said low frequency voltage;
a voltage controlled oscillator which generates an output clock in response to said control voltage;
a frequency divider which outputs a frequency divided clock and a frequency changed frame pulse by frequency dividing said output clock;
frame-pulse phase comparison means for outputting a difference signal by comparing phases of said selected frame pulse and said frequency changed frame pulse;
clock phase comparison means for outputting a reference clock having a duty factor corresponding to a phase difference of said selected clock and said frequency divided clock;
duty factor control means for outputting a pseudo clock by modifying a duty factor of said frequency divided clock;
and
clock selection means for outputting said phase control clock to said low-pass filter by selecting between said reference clock and said pseudo clock in response to said difference signal.

7 more elements

Dependencies are inferred from the claim text.