Semiconductor wafer for improved chemical-mechanical polishing over large area features
AssigneeMicron Technology, Inc.
InventorsGurtej Singh Sandhu, Chris Chang Yu
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AssigneeMicron Technology, Inc.
InventorsGurtej Singh Sandhu, Chris Chang Yu
Estimating the term…
The present invention is a semiconductor wafer, and a method of fabricating the semiconductor wafer, that reduces dishing over large area features in chemical-mechanical polishing processes. The semiconductor wafer has a substrate with an upper surface, a large area feature formed on the substrate, and a separation layer deposited on the substrate. The separation layer has a top surface and a cavity extending from the top surface towards the upper surface of the substrate. The large area feature is positioned in the cavity of the separation layer, and a support pillar is positioned in the cavity. In one embodiment, the pillar has a base positioned between components of the large area feature and a crown positioned proximate to a plane defined by the top surface of the separation layer. In operation, the pillar substantially prevents the polishing pad of a polishing machine from penetrating into the cavity beyond the top surface of the separation layer.
A method of fabricating a wafer for use in chemical-mechanical polishing of a layer of material over a large area feature on the wafer, comprising the steps of:
In chemical-mechanical polishing of semiconductor wafers, a method of polishing an upper layer of material from a wafer having a separation layer under the upper layer and a large area feature beneath in a cavity in the separation layer, the method comprising the steps of:
Dependencies are inferred from the claim text.