Self-refresh period adjustment circuit for semiconductor memory device

A self-refresh period adjustment circuit for a semiconductor memory device, said semiconductor memory device comprising a plurality of memory cell arrays, each of said memory cell arrays including a plurality of memory cells for storing data therein, comprising:

• a ring oscillator for generating a pulse signal with a fixed period for a self-refresh operation of said semiconductor memory device;
• leakage current detection means for detecting an amount of leakage current produced as charges stored in said memory cells are discharged;
• at least two temperature detection means for detecting a temperature variation of said semiconductor memory device, each of said at least two temperature detection means including voltage division means and comparison means, said voltage division means dividing a supply voltage and supplying the divided result as a reference signal to said comparison means, said comparison means comparing an output signal from said leakage current detection means with the reference signal from said voltage division means;
• and
• at least two frequency division means, each of said at least two frequency division means dividing a frequency of an output signal from said ring oscillator at a desired ratio in response to an output signal from a corresponding one of said at least two temperature detection means to adjust a self-refresh period of said semiconductor memory device.