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US 5,680,060 AGranted
Method of and circuit arrangement for terminating a line connected to a CMOS integrated circuit
AssigneeAlcatel
InventorsThomas Banniza, Helmut Preisach
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AssigneeAlcatel
InventorsThomas Banniza, Helmut Preisach
Estimating the term…
When high frequency signals are transmitted to an integrated circuit through a lfine, the line must have a matched terminal resistance located as closely as possible to its end. Every portion of the line without a matched terminal resistance, and each branch of the line, produces disturbing signal reflections. In modern housings of large-scale integrated circuits the terminals are only separated by 0.5 mm, and it becomes increasingly more difficult to connect a resistance as closely as possible to the terminal of the integrated circuit. According to the invention, a field effect transistor (T.sub.R), which functions as a terminal resistance, is located inside the integrated circuit. The value determined by the channel resistance is adjusted by means of a regulated control voltage, so that the effects of operating temperature, changes in the supply voltage and deviations in the integrated circuit caused by manufacturing processes have no effect on the resistance value needed for the line match.
A method of terminating a line connected to a CMOS integrated circuit in a resistance equal to the characteristic impedance of the line, characterized in that a field-effect transistor (T.sub.R) providing the terminating resistance is incorporated into the CMOS integrated circuit, and that the gate voltage applied to the field-effect transistor is adjusted via a measuring circuit (3) and a control circuit (4) by comparing a voltage generated outside the CMOS integrated circuit (6, 7) with a voltage generated within the CMOS integrated circuit (6, 7) to produce such an input signal for the control circuit (4) that the terminating resistance provided by the field-effect transistor (T.sub.R) is maintained at the required value regardless of manufacturing variations of the CMOS integrated circuit (6, 7), of variations in operating temperature, and of variations in supply voltage (V.sub.p).
A circuit arrangement for terminating a line connected to a CMOS integrated circuit in a resistance equal to the characteristic impedance of the line, characterized in that the line (Z) is connected to the drain-source path of a field effect transistor (T.sub.R) incorporated in the CMOS integrated circuit (6, 7) and providing the terminating resistance, the field-effect transistor (T.sub.R) having its gate terminal connected to the output of a control circuit (4) whose input is connected to a measuring circuit (3) which determines the difference between a voltage controlling the channel resistance of the field-effect transistor (T.sub.R) and a reference voltage (U.sub.ref).
Dependencies are inferred from the claim text.