System for executing high speed communication protocol processing by predicting protocol header of next frame utilizing successive analysis of protocol header until successful header retrieval

A communication control apparatus for connecting a computer system to a network, comprising:

• an interface circuit which provides an interface between said communication control apparatus and said computer system;
• a microprocessor for performing communication control processing;
• a local memory for storing programs and work data;
• a buffer memory for temporarily storing transmission and reception data;
• a DMA transfer circuit which performs data transfer between a first memory in said computer system and said buffer memory and protocol header transfer between said buffer memory and said local memory;
• a network controller for controlling transmission and reception of data to said network;
• header retrieval means for predicting a protocol header of a frame to be received next in correspondence to each of a plurality of connections set on said network by said computer system and retrieving a header corresponding to a protocol header of a received frame transferred by said DMA transfer means from said predicted protocol headers;
• a protocol analyzer for omitting successive analysis of the protocol header of said received frame in response to a successful retrieval by said header retrieval means, and for executing successive analysis of the protocol header of said received frame in response to an unsuccessful retrieval by said header retrieval means;
• a second memory, including a plurality of timer entries, for holding information necessary for timer control to the processor;
• a timer which performs timer count operation and timer notifying operation to said processor for the plurality of timer entries of said second memory;
• a timer controller for controlling an execution order of the timer notifying operation of a plurality of time-outs when the time-outs occur in entries of said second memory;
• and
• a buffer access arbiter circuit for arbitrating accesses to said buffer memory from said DMA transfer means and said network controller.

An integrated circuit for communication control, comprising:

• first interface means for connecting a higher-rank computer to communication control equipment;
• second interface means for connecting said communication control equipment to a network;
• third interface means for a buffer memory for temporarily storing transmission and reception data;
• fourth interface means for connecting a local bus to a processor of said communication control equipment;
• DMA transfer means for performing data transfer between a memory of said higher-rank computer and said buffer memory and performing protocol header transfer between said buffer memory and said fourth interface means;
• header retrieval means for retrieving a header corresponding to a protocol header of a received frame transferred by said DMA transfer means from protocol headers predicted corresponding to a plurality of connections set on said network by said computer system;
• a protocol analyzer for omitting successive analysis of the protocol header of said received frame in response to a successful retrieval by said header retrieval means, and for executing successive analysis of the protocol header of said received frame in response to an unsuccessful retrieval by said header retrieval means;
• and
• output means for outputting an identifier of a retrieved protocol header when retrieval by said header retrieval means is successful.