Multi-processor data processing system with control for granting multiple storage locks in parallel and parallel lock priority and second level cache priority queues

A storage lock management apparatus for use in a multiprocessor data processing system that includes a plurality of processors, each of which is for initiating storage lock operations for granting and releasing locks on portions of shared addressable memory, the system further including a plurality of intercoupled storage controllers, each providing access to a portion of addressable memory and intercoupled via a remote interface, wherein predetermined ones of the plurality of processors are directly coupled to a respective one of the storage controllers, the storage lock management apparatus comprising:

• a plurality of sets of lock-registers, a respective one of said sets in each of the storage controllers, wherein each said lock-register is associated with a respective one of the plurality of processors and is for indicating which of the portions of shared addressable memory is locked by said respective one of the plurality of processors;
• a plurality of lock priority circuits, a respective one of said lock priority circuits in each of the storage controllers, wherein each of said lock priority circuits is coupled to the predetermined ones of the processors that are directly coupled to the respective one of the storage controllers, whereby storage lock operations are received from the predetermined ones of the processors;
• a plurality of lock-register control circuits, a respective one of said lock-register control circuits in each of the storage controllers, and coupled to a respective one of said lock priority circuits and coupled to a respective one of said sets of lock-registers, whereby locks on the selectable portions of shared addressable memory are granted to the predetermined ones of the processors;
• a plurality of synchronization circuits, a respective one of said synchronization circuits in each of the storage controllers and coupled to a respective one of said lock priority circuits, coupled to a respective one of said lock-register control circuits, and coupled to the remote interface to synchronize presentation of a storage lock operation, initiated by one of the predetermined ones of the processors that are directly coupled to the respective one of the storage controllers, to said respective lock priority circuit with receipt of the storage lock operation by others of said second lock-register control circuits.

A storage lock management apparatus for use in a multiprocessor data processing system that includes a first plurality of processors coupled to a first storage controller, a second plurality of processors coupled to a second storage controller, wherein the first storage controller is coupled to the second storage controller via a remote interface, and first and second memory subsystems respectively coupled to the first and second storage controllers, wherein the first and second memory subsystems comprise the addressable memory space of the system, and the first and second memory subsystems are each accessible by the both the first and second plurality of processors, the storage lock management apparatus comprising:

• a first set of lock-registers, wherein each lock-register in said first set is associated with a first respective one of the first plurality of processors and the second plurality of processors and indicates which address within the addressable memory space of the system is locked by said first respective one of the processors;
• a second set of lock-registers, wherein each lock-register in said second set is associated with a second respective one of the first plurality of processors and the second plurality of processors and indicates which address within the addressable memory space of the system is locked by said second respective one of the processors;
• a first lock priority circuit coupled to each of the first plurality of processors for receiving storage lock operations from the first plurality of processors;
• a second lock priority circuit coupled to each of the second plurality of processors for receiving storage lock operations from the second plurality of processors;
• a first lock-register control circuit coupled to said first lock priority circuit and coupled to said first set of lock-registers for granting said storage lock operations from the first plurality of processors;
• a second lock-register control logic circuit coupled to said second lock priority circuit and coupled to said second set of lock-registers for granting said storage lock operations from the second plurality of processors;
• a first synchronization circuit coupled to said first lock priority circuit, coupled to said first lock-register control circuit, and coupled to the remote interface for synchronizing presentation of a storage lock operation, initiated by one of the first plurality of processors, to said first lock priority circuit with receipt of the storage lock operation provided by said second lock-register control circuit, whereby said first lock-register control circuit processes in parallel said storage lock operation initiated by said one of the first plurality of processors and said storage lock operation provided by said second lock-register control circuit;
• and
• a second synchronization circuit coupled to said second lock priority circuit, coupled to said second lock-register control circuit, and coupled to the remote interface for synchronizing presentation of a storage lock operation, initiated by one of the second plurality of processors, to said second lock priority circuit with receipt of the storage lock operation provided by said first lock-register control circuit, whereby said second lock-register control circuit processes in parallel said storage lock operation initiated by said one of the second plurality of processors and said storage lock operation provided by said first lock-register control circuit.

A parallel priority queue apparatus for use in managing storage locks in a multiprocessor data processing system that includes a plurality of processors, each for of issuing storage lock function codes for locking and releasing locks on selectable portions of shared addressable memory and memory access function codes for reading and writing to the addressable memory, the system further including two intercoupled storage controllers, each providing access to a portion of addressable memory, having a second-level cache, and intercoupled via a remote interface, wherein predetermined ones of the plurality of processors are directly coupled to a respective one of the storage controllers, the parallel priority queue apparatus in each of the storage controllers comprising:

• a second-level cache priority circuit coupled to the predetermined ones the processors and coupled to the second level cache, for of receiving memory access function codes from the predetermined ones of the processors;
• a lock priority circuit coupled to the predetermined ones of the processors and coupled to said second level cache priority circuit, for of receiving storage lock function codes directly from the predetermined ones of the processors and lock release function codes from said second-level cache priority circuit;
• a lock control circuit coupled to said lock priority circuit and coupled to the predetermined ones of the processors, for of receiving and processing storage lock function codes and granting and releasing locks on the selectable portions of addressable memory.

A storage lock management apparatus for use in a multiprocessor data processing system that includes a plurality of processors, each of which is for issuing storage lock function codes for locking and releasing locks on selectable portions of shared addressable memory and memory access function codes for reading and writing to the addressable memory, the system further including two intercoupled storage controllers, each having a second level cache and providing access to a predetermined portion of addressable memory and intercoupled via a remote interface, wherein predetermined ones of the plurality of processors are directly coupled to a respective one of the storage controllers, the storage lock management apparatus in each of the storage controllers comprising:

• a second-level cache priority circuit coupled to the predetermined ones the processors and coupled to the second level cache, for receiving memory access function codes from the predetermined ones of the processors;
• a lock priority circuit coupled to the predetermined ones of the processors and coupled to said second level cache priority circuit, for receiving storage lock function codes directly from the predetermined ones of the processors;
• a lock control circuit coupled to said lock priority circuit and coupled to the predetermined ones of the processors, for receiving and processing storage lock function codes and granting and releasing locks on the selectable portions of addressable memory;
• a set of lock-registers, wherein each lock-register is associated with a respective one of the plurality of processors and is for indicating which address is locked by the respective one of the processors;
• a lock-register control circuit coupled to said lock priority circuit and coupled to said set of lock-registers;
• a synchronization circuit coupled to said lock priority circuit, coupled to said lock-register control circuit, and coupled to the remote interface for synchronizing presentation of a storage lock operation, initiated by one of the predetermined ones of the processors that are directly coupled to the respective one of the storage controllers, to said lock priority circuit with receipt of the storage lock operation by a lock-register control circuit in the other storage controller.

A storage lock management apparatus for use in a multiprocessor data processing system that includes a plurality of processors, each of which is for issuing storage lock function codes for granting and releasing locks on selectable portions of shared addressable memory, the system further including two intercoupled storage controllers, each providing access to a portion of the shared addressable memory and intercoupled via a remote interface, wherein predetermined ones of the plurality of processors are directly coupled to a respective one of the storage controllers, the storage lock management apparatus in each of the storage controllers comprising:

• a set of lock-register means associated with the plurality of processors for indicating which of the selectable portions of shared addressable memory is locked by said associated plurality of processors;
• lock priority means coupled to the predetermined ones of the plurality of processors, for receiving storage lock function codes from the predetermined ones of the plurality of processors;
• lock-register control means coupled to said lock priority means, coupled to said lock-register means, and coupled to the remote interface, for receiving a lock function code directly from the remote interface and for processing said lock function code in parallel with a lock function code received from said lock priority means, and for granting and releasing locks on selectable portions of shared addressable memory to the predetermined ones of the plurality of processors;
• synchronization means coupled to said lock priority means, coupled to said lock-register control means, and coupled to the remote interface for synchronizing presentation to said lock priority means of a storage lock operation initiated by one of the predetermined ones of the plurality of processors that are directly coupled to the respective one of the storage controllers with receipt of said storage lock operation by a lock-register control means in the intercoupled storage controller.