Apparatus and method for a memory unit with a processor integrated therein

A processing system comprising:

• at least one external device, said at least one external device including a central processing unit;
• and
• an integrated circuit, wherein a package including said integrated circuit has the same external lead configuration as a standard memory package, said integrated circuit including;
• a memory unit functioning as memory for said at least one external device and having;
• a data memory, and
• a program memory, said program memory storing instructions;
• a processor coupled to said memory unit and having;
• an instruction decoder for retrieving and decoding instructions stored in said program memory;
• and
• a logic unit coupled to said instruction decoder for processing signal groups stored in said data memory in accordance with decoded instructions;
• a system bus coupling said memory unit and said at least one external device for exchanging instructions and data therebetween;
• and
• at least one control signal lead extending between said at least one external device and said integrated circuit for connecting said at least one external device to said processor;
• wherein said central processing unit and other external devices coupled to said system bus can directly access said memory during processing of signal groups by said processor.

A smart memory for use with an external device, wherein a package including said smart memory has the same external lead configuration as a standard memory package, said smart memory comprising:

• a storage unit providing memory for said external device, said storage unit including;
• a data memory storing signal groups, and
• a program memory, said program memory storing instructions;
• a processor connected to said storage unit;
• said processor including;
• an instruction decode unit for decoding said instructions, and
• a logic unit coupled to said instruction decode unit for processing signal groups in said data memory in accordance with said instructions stored in said program memory, wherein said storage unit and said processor are integrated in a single integrated circuit;
• and
• external leads providing apparatus for connecting said external device to said storage unit for an exchange of signal groups between said external device and said storage unit, wherein processing of signal groups by said processor is controlled by said external device.

A method of data processing by a processing device, said method comprising the steps of:

• providing an external lead configuration of a package including an integrated circuit to be the same as an external lead configuration of a standard memory package, said integrated circuit having a memory unit and a processor;
• storing instructions by said processing device in a program memory portion of said memory unit, said memory unit providing a memory for said processing device;
• storing data from said processing device in a data memory portion of said memory unit;
• and
• as a result of control signals from said processing device, causing said processor to decode instructions stored in said program memory portion of said integrated circuit and to process data stored in said data memory portion by said processor unit, processed data being stored in said data memory portion of said memory unit for retrieval by said processing device;
• wherein data and instructions stored in said memory unit of said integrated circuit are accessible by said processing device, control signals from said processing device causing said integrated circuit to operate in a first mode wherein only said processing device processes data from said memory unit, control signals from said processing device causing said integrated circuit to operate in a second mode wherein both said processing device and said processor process data in said data memory portion.

A data processing system comprising:

• a central processing unit;
• and
• an integrated device coupled to said central processing unit, wherein a package including said integrated circuit device has the same external lead configuration as a standard memory package, said integrated device including:
• a processor including a logic unit and an instruction decoder;
• and
• a storage unit connected to said central processing unit and providing a memory for said central processing unit, said storage unit connected to said processor for exchanging signal groups stored in said storage unit, said storage unit including a program memory portion for storing instructions, said instructions being decoded by said instruction decoder and applied to said logic unit, said logic unit processing signal groups according to decoded instructions;
• wherein said data processing system has two modes of operation, said central processing unit processing signal groups from said storage unit in a first mode of operation in response to control signals from said central processing unit, said processor and said central processing unit simultaneously processing signal groups from said data storage in response to control signals from said central processing unit in a second mode of operation.

For use in a data processing system having at least one connector for coupling memory modules to a processing unit, a smart memory module comprising:

• an external lead configuration for attachment to said connector, wherein a package including said smart memory module has the same external lead configuration as a standard memory package;
• a storage unit coupled to said external lead configuration, said processing unit interacting with said storage unit in the same manner as with a memory module, said data storage unit having a data memory for storing signal groups and a program memory for storing instructions;
• and
• a processor connected to said storage unit for exchanging signal groups therebetween, said processor including an instruction decoder coupled to said program memory for retrieving and decoding instructions stored in said program memory, said processor including a logic unit responsive to decoded instructions for processing signal groups from said storage unit, operation of said processor controlled by control signals from said processing unit.