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US 5,675,822 AGranted
Method and apparatus for a digital signal processor having a multiplierless computation block
AssigneeMotorola, Inc.
InventorBrian T. Kelley
Life of this patent
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Abstract
A digital signal processor having a multiplierless computation block (140) is accomplished by storing approximations of computed logarithms in memory (160, 162). When two pieces of data (114, 116) are received, the approximate logarithms, or logarithmic data (120, 128), for each of the pieces data are retrieved from memory. The logarithmic data (120, 128) is them summed to produce a resultant (136), wherein the resultant (136) is used to retrieve an inverse logarithmic approximation (180) that is stored in memory (170, 172) in a manner similar to that of the logarithmic approximations. The inverse logarithmic approximation (180) that results closely approximates the product of multiplying, or another arithmetic function, the two pieces of data (114, 116).
Claims28
A co-processor comprising:
- a control block that controls data routing in the co-processor;
- and
- a computation block operably coupled to the control block, wherein the computation block includes:
- a first logarithmic encoder that performs a first logarithmic approximation on first data to produce first logarithmic data, wherein routing of the first data to the first logarithmic encoder is controlled by the control block;
- a second logarithmic encoder that performs a second logarithmic approximation on second data to produce second logarithmic data, wherein routing of the second data to the second logarithmic encoder is controlled by the control block;
- an arithmetic block that combines the first logarithmic data and the second logarithmic data to produce a resultant that approximates an arithmetic function performed on the first data and the second data;
- and
- a logarithmic inverter operably coupled to the arithmetic block, wherein the logarithmic inverter performs an inverse-logarithmic approximation on the resultant.
5 more elements
A digital signal processor comprising:
- a program controller, wherein the program controller produces a plurality of control signals to control execution of an algorithm;
- an address generation unit operably coupled to the program controller, wherein the address generation unit generates address signals based on at least a first one of the plurality of control signals, wherein the address signals are used to retrieve a first data and a second data;
- and
- a multiplierless computation block operably coupled to the program controller, wherein the multiplierless computation block includes:
- a first logarithmic encoder that performs a first logarithmic approximation on the first data to produce first logarithmic data;
- a second logarithmic encoder that performs a second logarithmic approximation on the second data to produce second logarithmic data;
- an arithmetic block that combines, based on at least a second one of the control signals, the first logarithmic data and the second logarithmic data to produce a resultant that approximates an arithmetic function performed on the first data and the second data;
- and
- a logarithmic inverter operably coupled to the arithmetic block, wherein the logarithmic inverter performs an inverse-logarithmic approximation on the resultant.
6 more elements
A co-processor comprising:
- memory that stores most-significant logarithmic function values, least-significant logarithmic function approximations, most-significant inverse logarithmic function values, and least-significant inverse logarithmic function approximations, wherein the most-significant logarithmic function values and the least-significant logarithmic function approximations approximate values on a logarithmic error curve, and the most-significant inverse logarithmic function values and the least-significant inverse logarithmic function approximations approximate values on an inverse-logarithmic error curve;
- a logarithmic function block operably coupled to the memory, wherein the logarithmic function block generates at least a first address based on first data, wherein the at least a first address addresses a first one of the most-significant logarithmic function values and a first one of the least-significant logarithmic function approximations, and wherein the logarithmic function block generates at least a second address based on second data, wherein the at least a second address addresses a second one of the most-significant logarithmic function values and a second one of the least-significant logarithmic function approximations;
- wherein the logarithmic function block processes the first data, the second data, the first one of the most-significant logarithmic function values, the first one of the least-significant logarithmic function approximations, the second one of the most-significant logarithmic function values, and the second one of the least-significant logarithmic function approximations to perform a arithmetic function thereby producing a resultant;
- and
- wherein the logarithmic function block generates, based on the resultant, at least a third address for an inverse logarithmic function, wherein the third address addresses one of the most-significant inverse logarithmic function values and one of the least-significant inverse logarithmic function approximations, and wherein the logarithmic function block processes the resultant, the one of the most-significant inverse logarithmic function values, and the one of the least-significant inverse logarithmic function approximations to produce the inverse logarithmic function of the resultant.
2 more elements
Dependencies are inferred from the claim text.