Peripheral equipment control device

A peripheral equipment control LSI, which has two power dissipation modes different from each other, connected to a bus which is connected to a processor, said peripheral equipment control LSI comprising:

• a command detector for analyzing a command issued by a processor which is connected to said bus, whether the command is directed to the LSI or not;
• a command processor for processing a command directed to the LSI;
• and
• an internal clock controlling circuit for controlling power dissipation of said LSI in response to an output from at least one of said command detector and said command processor.

A peripheral equipment control LSI, which has two power dissipation modes where power dissipation in each mode is different, connected to a bus which is connected to a processor, said peripheral equipment control LSI comprising:

• a processing circuit for controlling peripheral equipment;
• and
• an internal clock controlling circuit for controlling power dissipation of said LSI,
• wherein said clock controlling circuit switches said LSI from a first power dissipation mode to a second power dissipation mode at the start of a controlling of the peripheral equipment by said processing circuit, and
• switches said LSI from the second power dissipation mode to the first power dissipation mode at the end of the controlling of the peripheral equipment by said processing circuit.

A peripheral equipment control LSI, which processes accesses from outside said LSI, comprising:

• an access detector for analyzing an access from outside of said LSI, whether the access is directed the LSI or not;
• an access processor for processing an access directed to the LSI;
• and
• an internal clock controlling circuit for controlling power dissipation of said LSI in response to an output from at least one of said access detector and said access processor.

An integrated circuit for controlling peripheral equipment power dissipation, comprising:

• a command detector for detecting a command from accesses issued by a processor;
• a command processor for processing said command;
• and
• a power dissipation controlling circuit for controlling power dissipation of the peripheral equipment in response to at least one of command detection by said command detector and the end of processing the command by said command processor.