Data processor using FIFO memories for routing operations to parallel operational units

A data processing device comprising

• a program memory for storing instruction data;
• a central instruction decoder connected to the program memory for decoding instruction data and supplying operation codes;
• an operational unit comprising a plurality of operational means executing the operation codes in parallel;
• and
• routing circuitry for routing the operation codes from the central instruction decoder to the operational units for parallel execution, the routing circuitry comprising at least one FIFO type memory, arranged between at least one of the operational units and the central instruction decoder, said at least one FIFO type memory being for providing operation codes, under control of the routing circuitry, to the at least one of the operational units,
• wherein the routing circuitry comprises means for controlling access to said the at least one FIFO type memory by means of aggregated signals derived from said at least one FIFO type memory and said at least one operational means and/or at least one other FIFO type memory;
• the aggregated signals being coupled to the instruction decoder.