Store software instrumentation package instruction

A method of storing instruction processor state information directly to a memory storage module with a single instruction command in a data processing system having an instruction processor and a second-level cache, the memory storage module having a plurality of memory storage locations, comprising the steps of:

• a. writing the instruction processor state information to an operand cache from an instruction processor state memory;
• b. storing the instruction processor state information to the second-level cache from the operand cache;
• c. reading an address field of a single store instruction processor state information command to determine a particular one of the plurality of memory storage locations within the memory storage module;
• and
• d. storing said instruction processor state information into said particular one of said plurality of memory storage locations from said second-level cache.

A method of storing instruction processor state information directly to a memory storage module with a single instruction command in a data processing system having an instruction processor and a second-level cache, the memory storage module having a plurality of memory storage locations, comprising the steps of:

• a. requesting the instruction processor to write the instruction processor state information to an operand cache from an instruction processor state memory;
• b. storing said instruction processor state information to the second-level cache from said operand cache;
• c. selecting a particular one of the plurality of memory storage locations within the memory storage module;
• and
• d. storing said instruction processor state information into said particular one of said plurality of memory storage locations from said second-level cache.

A method of storing instruction processor state information directly to a memory storage module with a single instruction command in a data processing system having an instruction processor and a second-level cache, the memory storage module having a plurality of memory storage locations, comprising the steps of:

• a. requesting the instruction processor to write the instruction processor state information to an operand cache from an instruction processor state memory;
• b. storing the instruction processor state information to the second-level cache from the operand cache;
• c. reading an address field of a single store instruction processor state information command to determine a particular one of the plurality of memory storage locations within the memory storage module;
• and
• d. storing said instruction processor state information into said particular one of said plurality of memory storage locations from said second-level cache.

An apparatus for storing instruction processor state information directly to a memory storage module with a single instruction command in a data processing system having an instruction processor and a second-level cache, the memory storage module having a plurality of memory storage locations, comprising:

• a. writing means coupled to an operand cache for writing the instruction processor state information to said operand cache from an instruction processor state memory;
• b. first storing means coupled to the second level cache and further coupled to said writing means for storing said instruction processor state information to said second-level cache from said operand cache;
• c. selecting means coupled to the plurality of memory storage locations within the memory storage module and further coupled to said first storing means for selecting a particular one of said plurality of memory storage locations within said memory storage module;
• and
• d. second storing means coupled to said particular one of said plurality of memory storage locations and further coupled to said selecting means for storing said instruction processor state information into said particular one of said plurality of memory storage locations from said second-level cache.

An apparatus for storing instruction processor state information directly to a memory storage module with a single instruction command in a data processing system having an instruction processor and a second-level cache, the memory storage module having a plurality of memory storage locations, comprising:

• a. writing means coupled to an operand cache for writing the instruction processor state information to said operand cache from an instruction processor state memory;
• b. first storing means coupled to the second level cache and further coupled to said writing means for storing said instruction processor state information to said second-level cache from said operand cache;
• c. reading means coupled to the plurality of memory storage locations within the memory storage module and further coupled to said first storing means for reading an address field of a single store instruction processor state information command to determine a particular one of said plurality of memory storage locations within said memory storage module;
• and
• d. second storing means coupled to said particular one of said plurality of memory storage locations and further coupled to said reading means for storing said instruction processor state information into said particular one of said plurality of memory storage locations from said second-level cache.

An apparatus for storing instruction processor state information directly to a memory storage module with a single instruction command in a data processing system having an instruction processor and a second-level cache, the memory storage module having a plurality of memory storage locations, comprising:

• a. requesting means coupled to an operand cache for requesting the instruction processor to write the instruction processor state information to said operand cache from an instruction processor state memory;
• b. first storing means coupled to the second level cache and further coupled to said requesting means for storing said instruction processor state information to said second-level cache from said operand cache;
• c. selecting means coupled to the plurality of memory storage locations within the memory storage module and further coupled to said first storing means for selecting a particular one of said plurality of memory storage locations within said memory storage module;
• and
• d. second storing means coupled to said particular one of said plurality of memory storage locations and further coupled to said selecting means for storing said instruction processor state information into said particular one of said plurality of memory storage locations from said second-level cache.

An apparatus for storing instruction processor state information directly to a memory storage module with a single instruction command in a data processing system having an instruction processor and a second-level cache, the memory storage module having a plurality of memory storage locations, comprising:

• a. requesting means coupled to an operand cache for requesting the instruction processor to write the instruction processor state information to said operand cache from an instruction processor state memory;
• b. first storing means coupled to the second level cache and further coupled to said requesting means for storing said instruction processor state information to said second-level cache from said operand cache;
• c. reading means coupled to the plurality of memory storage locations within the memory storage module and further coupled to said first storing means for reading an address field of a single store instruction processor state information command to determine a particular one of said plurality of memory storage locations within said memory storage module;
• and
• d. second storing means coupled to said particular one of said plurality of memory storage locations and further coupled to said reading means for storing said instruction processor state information into said particular one of said plurality of memory storage locations from said second-level cache.

In a data processing system having an instruction processor wherein the instruction processor maintains state information, the improvement comprising:

• a. means for reading the instruction processor state information;
• b. memory storage module having a plurality of memory storage locations;
• c. single store instruction processor state information command having an address field specifying a particular one of said plurality of memory storage locations said instruction processor state information is to be written to;
• d. means for reading said address field of said single store instruction processor state information command to determine said particular one of said plurality of memory storage locations within said memory storage module to store said instruction processor state information;
• e. reading said instruction processor state information;
• f. the instruction processor responsively coupled to an operand cache for writing the instruction processor state information to said operand cache;
• g. said operand cache responsively coupled to a second-level cache for storing the instruction processor state information to said second-level cache from said operand cache;
• h. reading said address field of said single store instruction processor state information command to determine said particular one of said plurality of memory storage locations within said memory storage module to store said instruction processor state information;
• and
• i. said second-level cache responsively coupled to said memory storage module for storing said instruction processor state information into said particular one of said plurality of memory storage locations within said memory storage module.