US 5,675,765 AGranted

Cache memory system with independently accessible subdivided cache tag arrays

AssigneeSun Microsystems, Inc.

InventorsAdam Malamy, Rajiv N. Patel, Norman M. Hayes

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Abstract

Two independently accessible subdivided cache tag arrays and a cache control logic is provided to a set associative cache system. Each tag entry is stored in two subdivided cache tag arrays, a physical and a set tag array such that each physical tag array entry has a corresponding set tag array entry. Each physical tag array entry stores the tag addresses and control bits for a set of cache lines. The control bits comprise at least one validity bit indicating whether the data stored in the corresponding cache line is valid. Each set tag array entry stores the descriptive bits for a set of cache lines which consists of the most recently used (MRU) field identifying the most recently used cache lines of the cache set. Each subdivided tag array is provided with its own interface to enable each array to be accessed concurrently but independently by the cache control logic which performs read and write operations against the cache. The cache control logic makes concurrent and independent accesses to the separate tag arrays to read and write the control and descriptive information in the tag entries. The accesses are grouped by type of operation to be performed and each type of accesses is made during predesignated time slots in an optimized manner to enable the cache control logic to perform certain selected read/write accesses to the physical tag array while performing other selected independent read/write accesses to the set tag array concurrently.

Claims14

Dependent claims

In a computer system comprising a central processing unit (CPU) and a main memory, a cache memory system comprising;

a cache memory coupled to the CPU and the main memory, said cache memory including a plurality of cache sets, each cache set having a plurality of cache lines to store a subset of data stored in said main memory;
a first cache tag array including a first plurality of cache tag entries corresponding to said cache sets of said cache memory, each cache tag of said plurality of cache tag entries includes identification and control information for each of said cache lines of a corresponding cache set of said cache memory, said first cache tag array further includes a first interface through which said identification and control information are accessed;
a second cache tag array includes a second plurality of cache tag entries corresponding to said cache sets of said cache memory and said first plurality of cache tag entries, each of said second plurality of cache tag entries includes descriptive information, which is different than said identification and control information, for said cache lines of said corresponding cache set of said cache memory, said second cache tag array further includes a second interface through which said descriptive information is accessed;
a cache controller, coupled to the CPU, the main memory, said cache memory and said first and second cache tag arrays, said cache controller controls read and write operations against said cache memory and performs accesses independent and concurrent to each other to said first and second cache tag arrays in order to read and write said identification, control and descriptive information in said first and second plurality of cache tag entries.

1 more element

In a computer system comprising a central processing unit (CPU) and a main memory, a method for caching a subset of data stored in said main memory, said method comprising the steps of:

storing said subset of data stored in said main memory in a plurality of cache lines of cache sets of a cache memory coupled to said CPU and said main memory;
storing a first plurality of cache tag entries in a first cache tag array, said first plurality of cache tag entries corresponding to said cache sets of said cache memory, each of said first plurality of cache tag entries includes identification and control information for each of said cache lines of a corresponding cache set of said cache memory, said first cache tag array further includes a first interface through which said identification and control information are accessed;
storing a second plurality of cache tag entries in a second cache tag array, said second plurality of cache tag entries corresponding to said cache sets of said cache memory and said first cache tag entries, each of said second plurality of cache tag entries includes descriptive information which is different than said identification and control information, for said cache lines of said corresponding cache set of said cache memory, said second cache tag array further includes a second interface through which said descriptive information is accessed;
controlling read and write operations against said cache memory, and said first and second cache tag arrays by a cache controller coupled to said CPU, said main memory, said cache memory and said first and second cache tag arrays, said cache controller performing accesses independent and concurrent to each other to said first and second cache tag arrays in order to read and write said identification, control and descriptive information in said first and second tag entries, said accesses being grouped by type of operation to be performed and accesses of an operation type group being made in predesignated time slots.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 08/604,687Filed 21 Feb 1996 · continuation
Priority: 29 Apr 1992
Granted: 7 Oct 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 12/123
Using replacement algorithms: with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
G06F 12/0831
Cache consistency protocols: using a bus scheme, e.g. with bus monitoring or watching means
G06F 12/0846
Multiple simultaneous or quasi-simultaneous cache accessing: cache with multiple tag or data arrays being simultaneously accessible
G06F
Computing and data processing