Processor having primary integer execution unit and supplemental integer execution unit for performing out-of-order add and move operations

A method of improving pipeline throughput, comprising:

• issuing a complex-integer operation to a primary integer execution unit capable of setting a flag result;
• issuing a reduced-integer operation to said primary integer execution unit and a supplemental integer execution unit incapable of setting a flag result, said reduced-integer operation conceptually being sequentially after said complex-integer operation, said reduced-integer operation requiring a register result and an optional flag result;
• issuing an operation requiring an effective address calculation, said operation requiring an effective address calculation conceptually being sequentially after said reduced-integer operation, said effective address calculation being dependent on said reduced-integer operation;
• calculating said reduced-integer operation's register result in said supplemental integer execution unit before said primary execution unit completes said reduced-integer operation;
• calculating said effective address before said primary execution unit completes said reduced-integer operation;
• and
• calculating said reduced-integer operation's flag result in said primary execution unit.