US 5,675,750 A · Interface having a bus master arbitrator for arbitrating occupation and release of a common bus between a host processor and a graphics system processor

Abstract

An interface for a high-performance graphics adapter is provided. In a computer system which includes a host processor, a coprocessor in the form of a graphics system processor, and memory addressable by both the host and coprocessors. An application computer program running on the host processor utilizes a graphics operating system, such as an Extended Graphics Array Input/Output System (XGA BIOS) to write graphics data in XGA format to the memory. A controller translates memory addresses generated by the XGA BIOS (and hence the host processor) into memory addresses recognized by the coprocessor. One or more graphics controllers selectively swap pixel data between Intel order and Motorola order and store the graphics data, into an XGA video-random-access memory (RAM) buffer. A back-end gate array parallel-serial converts input display data in units of designated pixel data, and the graphics data is displayed on a CRT.

Claims11

Dependent claims

An interface for interfacing a host processor to a graphics system processor, the host processor and graphics system processor being coupled to a common bus, the interface comprising:

a memory having at least a first area accessible by the host processor and a second area accessible by the graphics system processor;
a computer program operating on the host processor for generating memory addresses and data elements associated with the memory addresses;
a memory address translator for translating addresses of the first area into addresses of the second area;
a graphics controller for storing the data elements into memory locations defined by the translated memory addresses;
and
a bus master arbitrator for arbitrating occupation and release of the common bus between the host processor and the graphics system processor, the bus master arbitrator including means for producing a retry signal to the graphics system processor in response to a condition that the common bus is busy, and means for counting occurrences of the retry signal and for producing a bus fault signal to the graphics system processor when the count value reaches a predetermined value.

3 more elements

Dependencies are inferred from the claim text.

Interface having a bus master arbitrator for arbitrating occupation and release of a common bus between a host processor and a graphics system processor

Life of this patent

Interface having a bus master arbitrator for arbitrating occupation and release of a common bus between a host processor and a graphics system processor

Life of this patent

Abstract

Claims11