Method and apparatus for controlling show cycles in a data processing system

A method for operating a data processing system, the data processing system having a first internal bus, having a second internal bus, and having an external bus, the external bus providing information external to the data processing system, the method comprising the steps of:

• performing a first plurality of internal bus cycles on the first internal bus;
• performing a second plurality of internal bus cycles on the second internal bus;
• if a first storage circuit stores a first value, providing all of the first plurality of internal bus cycles on the external bus;
• if the first storage circuit stores a second value, providing none of the first plurality of internal bus cycles on the external bus;
• if the first storage circuit stores a third value, providing a first portion of the first plurality of internal bus cycles on the external bus;
• and
• if a second storage circuit stores a fourth value, providing a first portion of the second plurality of internal bus cycles on the external bus.

A data processor, comprising:

• an external bus for providing information external to the data processor;
• an internal bus for performing a first plurality of internal bus cycles which are provided to said external bus during non-test operation, and for performing a second plurality of internal bus cycles which are not provided to said external bus during non-test operation;
• a storage circuit, said storage circuit storing a control value;
• and
• control circuitry, coupled to said internal bus, to said external bus, and to said storage circuit, said control circuitry receiving the control value from said storage circuit and monitoring the second plurality of internal bus cycles, in response to the control value said control circuitry providing selected ones of the second plurality of internal bus cycles on said external bus.

A method for operating a data processing system, the data processing system having an internal bus and having an external bus, the external bus providing information external to the data processing system, the internal bus having an internal bus data transfer speed, the external bus having an external bus data transfer speed, the method comprising the steps of:

• performing a plurality of internal bus cycles on the internal bus;
• if a storage circuit stores a first value, providing all of the plurality of internal bus cycles on the external bus;
• if the storage circuit stores a second value, providing none of the plurality of internal bus cycles on the external bus;
• if the storage circuit stores a third value, providing a first portion of the plurality of internal bus cycles on the external bus;
• and
• if external bus data transfer speed is greater than the internal bus data transfer speed, preventing a new bus cycle from beginning on the internal bus when at least one of the plurality of internal bus cycles is waiting to be provided on the external bus.