US 5,675,729 A · Method and apparatus for performing on-chip measurement on a component

Abstract

The system of the present invention includes programmable logic to generate watchpoint traps which cause a branch to determined trap code and breakpoint signals which cause the stopping of the system dock. Furthermore, the system can measure system performance criteria. The logic is flexible and easy to program, but sophisticated in application to provide a variety of criteria that trigger on events which in turn increment the counters. In the preferred embodiment, the system includes two counters and trigger decode logic to increment the counters. Each counter is independently programmable to enable the user to determine such performance information as average latency, which is a combination of one counter counting the number of occurrences of a particular event and a second counter counting the duration of the events. Both counters can be programmed to measure on edges or levels of signals. In addition, the triggers can be used in a cascaded structure, wherein the first counter is used to generate a trigger which may be further qualified by the second counter. Using this implementation, a more flexible counting strategy is provided. Furthermore, by using the two counters in a cascaded fashion, the occurrence on one type of event can be used to monitor the occurrence of a second type of event in order to determine the occurrence of a combination of events. In addition, both watchpoint traps and breakpoint signals can be generated based upon the occurrence of a variety of events internal to the component and not easily accessible during execution by the user.

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Claims46

Dependent claims

In an integrated component located on a chip, said integrated component comprising a processor and an apparatus for detecting events which occur on the integrated component, said apparatus for detecting events comprising:

trigger decode logic comprising;
a plurality of inputs for receiving signals indicative of occurrences of events, and
a first event select register comprising data which identifies selectively events to generate a first output trigger signal, said trigger decode logic outputting a first output trigger signal when at least one event identified by the first event select register occurs;
counter logic for counting a number of output trigger signals generated comprising;
an input coupled to receive the first output trigger signal, and a count incrementor for selectively incrementing a first count for each first output trigger signal received.

2 more elements

trigger decode logic comprising;
a plurality of inputs for receiving signals indicative of occurrences of events, and
a first event select register comprising data which identifies selectively events to generate a first output trigger signal, said trigger decode logic outputting the first output trigger signal when at least one event identified by the first event select register occurs,
a first level detector for detecting a duration of at least one event,
a first edge detector for detecting the occurrences of at least one event, and
a first edge/level select for selecting the first output trigger signal to be selectively responsive to an occurrence of at least one event or to a duration of at least one event;
and
counter logic for counting a number of first output trigger signals generated comprising;
an input coupled to receive the first output trigger signal, and
a count incrementor for selectively incrementing a first count for each first output trigger signal received.

7 more elements

Dependencies are inferred from the claim text.

Description5,875 words

Summary1,455 words

#1. Field of the Invention

#The present invention relates to the measurement of performance of computer systems. More particularly, the present invention relates to the measurement of performance of operation of high speed, highly integrated processors.

#2. Art Background

Brief description of the drawings7 figures

#The objects, features and advantages of the present invention will be apparent to one skilled in the art from the following detailed description in which:

#FIG. 1a is a block diagram illustration of the debug and performance monitoring logic of the present invention and FIG. 1b is a block diagram illustrating exemplary logic to operate the triggers in a cascade mode utilized in one embodiment of the present invention.

#FIG. 2 is a block diagram illustrating the trigger decode logic utilized in the logic of the present invention.

Detailed description4,210 words

#In the following description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the present invention. In other instances, electrical structures and circuits are shown in block diagram form in order not to obscure the present invention unnecessarily.

#The system and method of the present invention provides a flexible and sophisticated counting mechanism for monitoring events which occur in a highly integrated electrical component, such as a processor component. A block diagram of one embodiment of the logic of the present invention is shown in FIG. 1a. Trigger decode logic 10 receives as input the events which may, depending upon the programmed state of the trigger decode logic, generate an output trigger to increment the values store in the counters registers 20, 60. In the present embodiment, the trigger decode logic includes logic to generate a first trigger, Trigger A, and a second trigger, Trigger B. As will be explained subsequently, these triggers can be used in combination with one another to provide average measurement as well as cascaded or dual measurements.

#The counter logic further includes the counter A register 20 and a multiplexor 25, to select, based upon the trigger A input, whether the counter is to be updated with an incremented value, or be maintained at its current value. In order to determine when the counter register 20 has reached its counted value, it is preferred that the counter register 20 is initially loaded through write.sub.-- select multiplexor 30 with a negative value (e.g., 2's complement) of the count that the register is to achieve prior to generating an output signal indicative of a certain state of the component. Thus, the output signal is simply an overflow of the counter register. This output signal is subsequently output to generate watchpoint triggers and breakpoint triggers for software and hardware debug processing.

Facts

Application

08/699,199Filed 19 Aug 1996 · continuation

Priority

22 Oct 1993

Granted

7 Oct 1997

Term ended

22 Oct 2013

Estimated · how

20 years from earliest known nonprovisional domestic filing. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination. Patent term adjustment is unavailable; no adjustment was added.

Classification5 codes

G06F 11/3409
Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of…:…
G06F 11/348
Performance evaluation by tracing or monitoring: circuit details, i.e. tracer hardware
G06F 2201/86
Indexing scheme relating to error detection, to error correction, and to monitoring: event-based monitoring
G06F 2201/88
Indexing scheme relating to error detection, to error correction, and to monitoring: monitoring involving counting

Method and apparatus for performing on-chip measurement on a component

Life of this patent

Method and apparatus for performing on-chip measurement on a component

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims46

Description5,875 words

Drawings

Classification5 codes

Life of this patent

Description5,875 words