Apparatus and method identifying false timing paths in digital circuits

#The present invention pertains to the field of digital circuit design, layout, and optimization. More particularly, the present invention relates to an apparatus and method for identifying false timing paths in digital circuits.

#Computers are being used in computer aided design and computer aided-manufacturing (CADCAM) applications as a tool for engineers and designers. One application for which computers have been utilized is in the design, layout, and optimization process for digital circuits. Before an integrated circuit (IC) is actually fabricated, its circuit design can be simulated on a computer and tested. Errors in the design can be identified and corrected without actually fabricating and testing the chip. This minimizes development cost and speeds up time to market. Furthermore, computers are being used to optimize IC layout in order to reduce the die size. Reducing the die size is important because a smaller die size means that more dies (i.e., chips) can be fabricated from a given wafer. This directly translates into less manufacturing cost per die.

#Prior art IC test tools currently have the capability of identifying the false timing paths. A false timing path is defined as a timing path which is never exercised logically. In other words, no matter what combination of signals are input to the IC, the false timing path is never implemented. The reason why identifying false timing paths is important because once these false timing paths are known, they do not have to be optimized. Sometimes, circuit designs can have hundreds of false timing paths. Not having to optimize all of these false timing paths reduces design effort, and shortens design cycles.

#The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

#FIG. 1 shows a typical computer system used for identifying false timing paths according to the present invention.

#FIG. 2 shows the flow for the false path identification process of the present invention.

#An apparatus and method for identifying false timing paths is described. In the following description, for purposes of explanation, numerous specific details are set forth, such as gates, subroutines, netlists, etc., in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown only in block diagram form to avoid unnecessary details obscuring the present invention.

#FIG. 1 shows a typical computer-based system for identifying false timing paths according to the present invention. Shown is a computer 101 which comprises three major components, including input/output (I/O) circuit 102, the central processing unit (CPU) 103 and memory 104. These latter two elements are found in most general purpose computers and almost all special purpose computers. In fact, the several elements contained within computer 101 are intended to be representative of this broad category of data processors. Particular examples of suitable data processors to fill the role of computer 101 include machines manufactured by Sun Microsystems, Inc., Mountain View, Calif. Other computers having like capabilities may of course be adapted in a straightforward manner to perform the functions described below.

#Also shown in FIG. 1 is an input device 105, shown in typical embodiment as a keyboard. It should be understood, however, that the input device may actually be a card reader, magnetic or paper tape reader, or other well-known input device (including, of course, another computer). A mass memory device 106 is coupled to the I/O circuit 102 and provides additional storage capability for the computer 101. The mass memory may include other programs and the like and may take the form of a magnetic or paper tape reader or other well-known device. It will be appreciated that the data retained within mass memory 106, may, in appropriate cases, be incorporated in standard fashion into computer 101 as part of memory 104.