US 5,675,726 A · Flexible parity generation circuit

Abstract

A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs switching means to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO. Thus, the system can be adapted to generate parity information for very large blocks of data in a single channel.

Claims24

Dependent claims

A method for generating redundancy blocks associated with a multiplicity of data blocks for each of a plurality of data channels in conjunction with a data block modification operation, said method comprising the steps of:

logically partitioning a memory device into a like plurality of data storage locations corresponding to said plurality of data channels;
storing a first data block and associated first at least one redundancy block from a first of said plurality of data channels in a first of said data storage locations;
interleaving and storing a second data block and associated second at least one redundancy block from a second of said plurality of data channels in a second of said data storage locations timewise during the storing of said first data block and said associated first at least one redundancy block;
modifying said first data block to a modified first data block;
inputting said modified first data block to said first of said data storage locations;
and computing an associated modified first at least one redundancy block based upon said first data block, said associated first at least one redundancy block, and said modified first data block.

3 more elements

A multi-channel redundancy block generation circuit comprising:

an input data bus for receiving data blocks and associated redundancy blocks from a plurality of logical data channels;
a memory device logically partitioned into a like plurality of data storage locations, each corresponding to one of said plurality of logical data channels;
a switching circuit operatively coupled to said data input bus for selectively applying said data blocks and associated redundancy blocks from said plurality of logical data channels in a timewise interleaved manner to at least one data input of said memory device;
an address selector circuit operatively coupled to an address input of said memory device for directing said data blocks and associated redundancy blocks from said plurality of logical data channels to a desired location in a corresponding one of said plurality of data storage locations in said memory device;
a multi-input redundancy block generator coupled to at least one output of said memory device for generating at least one redundancy block in response to data maintained in a portion of a particular one of said plurality of data storage locations;
and
an output data bus coupled to receive an output of said multi-input redundancy block generator for transferring said at least one redundancy block to a corresponding one of said plurality of logical data channels.

4 more elements

Dependencies are inferred from the claim text.

Flexible parity generation circuit

Life of this patent

Flexible parity generation circuit

Life of this patent

Abstract

Claims24