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US 5,675,620 AGranted
High-frequency phase locked loop circuit
AssigneesAT&T Global Information Solutions Company, Hyundai Electronics America, Symbios Logic Inc.
InventorDao-Long Chen
Life of this patent
Estimating the term…
Abstract
A high-frequency phase locked loop circuit effectively increases the maximum frequency associated with the CMOS technology. The circuit includes a first phase-locked loop sub-circuit having an input and an output, a second phase-locked loop sub-circuit having an input coupled to the input of the first phase-locked loop circuit and an output, and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop sub-circuits and an output. The first and second phase-locked loop may be arranged in parallel or in a master/slave relationship.
Claims23
A circuit comprising:
- a first phase-locked loop circuit having an input and an output;
- a second phase-locked loop circuit having an input coupled to the input of the first phase-locked loop circuit and an output;
- and
- an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop circuits and an output, wherein the output of the exclusive-OR circuit provides a clock signal.
1 more element
A circuit comprising:
- a first phase-locked loop circuit having an input and an output;
- a second phase-locked loop circuit having an input coupled to the input of the first phase-locked loop circuit and an output;
- and
- an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop circuits and an output, wherein the inputs of the first and second phase-locked loop circuits are coupled to a crystal which produces a signal having a predetermined frequency;
- wherein the output of the exclusive-OR circuit provides an output signal having an output frequency which is a multiple of the predetermined frequency;
- and wherein the circuit comprises CMOS transistors and the output frequency is greater than 500M Hz.
3 more elements
A circuit comprising:
- a first phase-locked loop circuit having an input and an output;
- a second phase-locked loop circuit having an input coupled to the input of the first phase-locked loop circuit and an output;
- and
- an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop circuits and an output, wherein the inputs of the first and second phase-locked loop circuits are coupled to a crystal which produces a signal having a predetermined frequency;
- wherein the output of the exclusive-OR circuit provides an output signal having an output frequency which is a multiple of the predetermined frequency;
- and wherein the circuit comprises CMOS transistors and the output frequency is greater than 1 GHz.
3 more elements
A circuit comprising:
- a first phase-locked loop circuit having an input and an output;
- a second phase-locked loop circuit having an input coupled to the input of the first phase-locked loop circuit and an output;
- and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop circuits and an output;
- wherein the first phase-locked loop circuit comprises:
- a divide-by-N circuit having the input to the first phase-locked loop circuit and an output;
- a phase detector having first and second inputs and an output, wherein the first input is coupled to the output of the divide-by-N circuit;
- a charge pump having an input coupled to the output of the phase detector and an output;
- a loop filter having an input coupled to the output of the charge pump and an output;
- a voltage-controlled oscillator having an input coupled to the output of the loop filter and an output coupled to the first input of the exclusive-OR circuit;
- and
- a divide-by-M circuit having an input coupled to the output of the voltage-controlled oscillator and an output coupled to the second input of the phase detector;
- and wherein the second phase-locked loop circuit comprises:
- a divide-by-O circuit having the input to the second phase-locked loop circuit and an output;
- a phase detector having first and second inputs and an output, wherein the first input is coupled to the output of the divide-by-O circuit;
- a charge pump having an input coupled to the output of the phase detector and an output;
- a loop filter having an input coupled to the output of the charge pump and an output;
- a voltage-controlled oscillator having an input coupled to the output of the loop filter and an output coupled to the second input of the exclusive-OR circuit;
- and
- a divide-by-P circuit having an input coupled to the output of the voltage-controlled oscillator and an output coupled to the second input of the phase detector;
- wherein the inputs of the first and second phase-locked loop circuits are coupled to a crystal which produces an input signal having a predetermined input frequency;
- wherein ratios M:N and P:O are equal to a common ratio;
- and wherein the output of the exclusive-OR circuit provides an output signal having an output frequency which is equal to the input frequency multiplied by twice the common ratio.
19 more elements
A circuit comprising:
- a first phase-locked loop circuit having an input and an output;
- a second phase-locked loop circuit having an input coupled to the input of the first phase-locked loop circuit and an output;
- and
- an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop circuits and an output, wherein the first phase-locked loop circuit comprises:
- a divide-by-N circuit having the input to the first phase-locked loop circuit and an output;
- a phase detector having first and second inputs and an output, wherein the first input is coupled to the output of the divide-by-N circuit;
- a charge pump having an input coupled to the output of the phase detector and an output;
- a loop filter having an input coupled to the output of the charge pump and an output;
- a voltage-controlled oscillator having an input coupled to the output of the loop filter and an output coupled to the first input of the exclusive-OR circuit;
- and
- a divide-by-M circuit having an input coupled to the output of the voltage-controlled oscillator and an output coupled to the second input of the phase detector,
- wherein the first phase-locked loop circuit comprises a master phase-locked loop circuit, and wherein the second phase-locked loop circuit comprises a slave phase-locked loop circuit which is clocked by the master phase-locked loop circuit.
9 more elements
A circuit comprising:
- a first phase-locked loop circuit having an input and an output;
- a second phase-locked loop circuit having an input coupled to the input of the first phase-locked loop circuit and an output;
- and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop circuits and an output;
- wherein the first phase-locked loop circuit comprises:
- a divide-by-N circuit having the input to the first phase-locked loop circuit and an output;
- a phase detector having first and second inputs and an output, wherein the first input is coupled to the output of the divide-by-N circuit;
- a charge pump having an input coupled to the output of the phase detector and an output;
- a loop filter having an input coupled to the output of the charge pump and an output;
- a voltage-controlled oscillator having an input coupled to the output of the loop filter and an output coupled to the first input of the exclusive-OR circuit;
- and
- a divide-by-M circuit having an input coupled to the output of the voltage-controlled oscillator and an output coupled to the second input of the phase detector, wherein the first phase-locked loop circuit comprises a master phase-locked loop circuit, and wherein the second phase-locked loop circuit comprises a slave phase-locked loop circuit which is clocked by the master phase-locked loop circuit;
- wherein the second phase-locked loop circuit comprises:
- a divide-by-O circuit having the input to the second phase-locked loop circuit and an output;
- a phase detector having first and second inputs and an output, wherein the first input is coupled to the output of the divide-by-O circuit;
- a charge pump having an input coupled to the output of the phase detector and an output;
- a loop filter having an input coupled to the output of the charge pump and an output;
- a delay circuit having a first input coupled to the output of the loop filter, a second input coupled to the output of the voltage-controlled oscillator of the first phase-locked loop circuit, and an output coupled to the second input of the exclusive-OR circuit;
- and
- a divide-by-P circuit having an input coupled to the output of the delay circuit and an output coupled to the second input of the phase detector.
16 more elements
A CMOS phase-locked loop circuit comprising:
- a first phase-locked loop sub-circuit having an input and an output, including
- a divide-by-N circuit having the input to the first phase-locked loop sub-circuit and an output;
- and
- a first circuit including
- a phase detector having a first input coupled to the output of the divide-by-N circuit, and a second input;
- and
- a divide-by-M circuit having an input coupled to the output of the first phase-locked loop sub-circuit, and an output coupled to the second input of the phase detector;
- a second phase-locked loop sub-circuit having an input coupled to the input of the first phase-locked loop sub-circuit and an output, including
- a divide-by-N circuit having the input to the second phase-locked loop sub-circuit and an output;
- and
- a second circuit including
- a phase detector having a first input coupled to the output of the divide-by-N circuit, and a second input;
- and
- a divide-by-M circuit having an input coupled to the output of the second phase-locked loop sub-circuit, and an output coupled to the second input of the phase detector;
- and
- an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop sub-circuits and an output;
- wherein the output of the exclusive-OR circuit provides an output signal having an output frequency which is equal to an input frequency of an input signal applied to the inputs of the first and second phase-locked loop sub-circuits multiplied by twice the ratio M:N.
14 more elements
A CMOS circuit comprising:
- a master phase-locked loop sub-circuit having an input and an output, including
- a divide-by-N circuit having the input to the master phase-locked loop sub-circuit and an output;
- and
- a first circuit including
- a phase detector having a first input coupled to the output of the divide-by-N circuit, and a second input;
- a voltage-controlled oscillator having an output coupled to the output of the master phase-locked loop sub-circuit;
- and
- a divide-by-M circuit having an input coupled to the output of the voltage-controlled oscillator and an output coupled to the second input of the phase detector;
- a slave phase-locked loop sub-circuit having an input coupled to the input of the master phase-locked loop sub-circuit and an output, including
- a divide-by-N circuit having the input to the slave phase-locked loop sub-circuit and an output;
- and
- a second circuit including
- a phase detector having a master input coupled to the output of the divide-by-N circuit, and a second input;
- a delay circuit having an input coupled to the output of the voltage-controlled oscillator of the master phase-locked loop sub-circuit, and an output coupled to the output of the slave phase-locked loop sub-circuit;
- and
- a divide-by-M circuit having an input coupled to the output of the delay circuit and an output coupled to the second input of the phase detector;
- and
- an exclusive-OR circuit having master and second inputs coupled to the outputs of the master and slave phase-locked loop sub-circuits and an output;
- wherein the output of the exclusive-OR circuit provides an output signal having an output frequency which is equal to an input frequency of an input signal applied to the inputs of the master and slave phase-locked loop sub-circuits multiplied by twice the ratio M:N.
16 more elements
A system comprising:
- a crystal which produces an output signal having an output frequency;
- a phase-locked loop circuit comprising:
- a first phase-locked loop sub-circuit having an input coupled to the crystal output signal, and an output;
- a second phase-locked loop sub-circuit having an input coupled to the input of the first phase-locked loop sub-circuit and an output;
- and
- an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop sub-circuits and an output which produces an output signal having an output frequency which is a predetermined multiple of the output frequency;
- and
- a logic element coupled to the output of the exclusive-OR circuit.
5 more elements
A method for producing a clock signal having a frequency comprising the steps of:
- producing a first signal, having half of the frequency, by a first phase-locked loop circuit;
- producing a second signal, having half the frequency and differing ninety degrees in phase from the first signal, by a second phase-locked loop circuit;
- and
- coupling the first and second signals to an exclusive-OR logic element.
1 more element
A circuit comprising:
- a first phase-locked loop circuit having an input and an output;
- a second phase-locked loop circuit having an input coupled to the input of the first phase-locked loop circuit and an output;
- and
- an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop circuits and an output, wherein a first signal at the first input of the exclusive-OR circuit and a second signal at the second input of the exclusive-OR circuit differ in phase by about ninety degrees.
1 more element
Dependencies are inferred from the claim text.