US 5,675,546 A · On-chip automatic procedures for memory testing

Abstract

The on-chip endurance test (Autocycle) and the parametric characterization test (Auto VccMax/Min) of this invention save test time and hardware by performance automatically on the memory chip upon transmittal of a single command (CONTROL CODE) to the chip from the tester. The automated test procedures of this invention run faster because the on-chip tester requires fewer externally issued commands (CONTROL CODEs) and requires fewer external status checks. The procedures of this invention permit the external tester to have a smaller number of input/output pins (CONTROL), decreasing the cost of the external test hardware. Specifically, the endurance test (Autocycle), automatically cycles the memory chip through any combination of programming, erasing, and/or compaction operations until either a failure has been detected or the required number of the test cycles has been completed. The parametric characterization test (AutoVccMax/Min) determines automatically the maximum supply voltage and/or the minimum supply voltage for data operation of the memory chip. The endurance test (Autocycle) uses a microsequencer (MC) and an on-chip built-in-logic-block-observation (BILBO) register to check information in a control-read-only memory (CROM). Output data from the control-read-only memory is latched in a BILBO register enhanced for use as a counter for large count. During the endurance test (Autocycle), the microsequencer (MC), using enhanced counter, monitors the number of on-chip controlled endurance test cycles. During the parametric characterization test (AutoVccMax/Min), an on-chip digital-analog converter (DAC) causes stepped changes in the supply voltage (Vcc) furnished to both the data cells (10) and the reference cells (10) of the memory.

Claims18

Dependent claims

A method for performing an endurance test on a memory array formed on a single integrated-circuit chip in response to microcodes from an external source, said method comprising:

forming a control-read-only-memory on said chip;
programming instructions for performing said endurance test in said control-read-only-memory;
forming a microsequencer on said chip to perform, in response to said microcodes from said external source, said endurance test of said memory array according to said instructions programmed in said control-read-only-memory, said microsequencer including a test multiplexer for receiving microcodes from said external source and for coupling a first signal to an instruction decoder, said instruction decoder also receiving an operation code from said control-read-only-memory, said instruction decoder controlling a subroutine stack, including a program counter multiplexer for receiving said operation code, for receiving a second signal from said subroutine stack, and for receiving a third signal from an incrementer, said program counter multiplexer furnishing a fourth signal to said control-read-only-memory, said incrementer taking said fourth signal from said program counter multiplexer and, from said fourth signal, generating said third signal as a next microcode address;
forming at least one built-in-logic-block-observation register on said chip to check information in said control-read-only memory and to latch output data from said control-read-only memory, said built-in-logic-block-observation register usable as a counter;
causing said microsequencer to receive an endurance test command;
and
using said built-in-logic-block-observation register to count the number of endurance test cycles.

4 more elements

A method for performing a parametric data test on a memory array formed on a single integrated-circuit chip in response to microcodes from an external source, said method comprising:

forming a control-read-only-memory on said chip;
programming instructions for performing said parametric data test in said control-read-only-memory;
and
forming a microsequencer on said chip to perform, in response to said microcodes from said external source, said parametric data test of said memory array according to said instructions programmed in said control-read-only-memory, said microsequencer including a test multiplexer for receiving microcodes from said external source and for coupling a first signal to an instruction decoder;
said instruction decoder also receiving an operation code from said control-read-only-memory, said instruction decoder controlling a subroutine stack, including a program counter multiplexer for receiving said operation code, for receiving a second signal from said subroutine stack, and for receiving a third signal from an incrementer, said program counter multiplexer furnishing a fourth signal to said control-read-only-memory;
said incrementer taking said fourth signal from said program counter multiplexer and, from said fourth signal, generating said third signal as a next microcode address;
forming a digital-analog converter on said chip to cause stepped changes in supply voltage furnished to data cells of said memory and to reference cells of said memory;
causing said microsequencer to receive a parametric data test command;
and
performing said parametric data test.

7 more elements

A method for monitoring the number of on-chip, particular-type tests on a memory array formed on a single integrated-circuit chip in response to microcodes from said external source, said method comprising:

forming a control-read-only-memory on said chip;
programming instructions for performing sequential said on-chip tests in said control-read-only-memory;
and
forming a microsequencer on said chip to monitor, in response to said microcodes from said external source, said number of said on-chip tests of said memory array according to said instructions programmed in said control-read-only-memory, said microsequencer including a test multiplexer for receiving microcodes from said external source and for coupling a first signal to an instruction decoder;
said instruction decoder also receiving an operation code from said control-read-only-memory, said instruction decoder controlling a subroutine stack, including a program counter multiplexer for receiving said operation code, for receiving a second signal from said subroutine stack, and for receiving a third signal from an incrementer, said program counter multiplexer furnishing a fourth signal to said control-read-only-memory, said incrementer taking said fourth signal from said program counter multiplexer and, from said fourth signal, generating said third signal as a next microcode address;
forming as part of said microsequencer an enhanced m-Bit counter and a separate end-of-count detector on said chip, said m-Bit counter receiving an initial count and a signal from said external source and transmitting count information to said separate end-of-count detector and program counter multiplexer, said separate end-of-count detector furnishing a scanning output.

3 more elements

Dependencies are inferred from the claim text.

On-chip automatic procedures for memory testing

Life of this patent

On-chip automatic procedures for memory testing

Life of this patent

Abstract

Claims18