Method and circuit for testing memories in integrated circuit form

An integrated circuit, comprising:

• an array of memory cells arranged in rows and columns;
• one or more precharging and reading subcircuits, each operatively connected to at least one respective column of said array of memory cells, and each comprising:
• a current-to-voltage converter having an input terminal connected to be driven by a current signal from said respective column, and having an output terminal connected to provide a voltage signal corresponding to said current signal when an enable signal is active,
• a precharging circuit connected to selectably drive said voltage signal toward a power supply voltage,
• a read circuit connected to detect the voltage of said voltage signal and provide a corresponding digital output through an output register,
• a first bypass transistor connected to selectably bypass said read circuit and said output register, but not said current-to-voltage converter, under control of a first test-mode control signal;
• and
• an output terminal operatively connected to said digital output;
• wherein said precharging circuit is controlled in dependence both on a clock signal and also on a second test-mode control signal.

An integrated circuit memory, comprising:

• an array of memory cells;
• and one or more precharging and reading subcircuits, each selectably connected to multiple respective multi-cell portions of said array of memory cells, and each comprising:
• an impedance element having an input terminal connected to be driven by said respective portion of said array, and having an output terminal connected to provide a voltage signal which indicates signals received at said input terminal;
• a precharging circuit connected to selectably drive said voltage signal toward a power supply voltage,
• a read circuit connected to detect the voltage of said voltage signal and provide a corresponding digital output,
• a first bypass transistor connected to selectably bypass said read circuit, but not said impedance element, under control of a first test-mode control signal;
• and
• an output terminal operatively connected to said digital output;
• wherein said precharging circuit is controlled in dependence both on a clock signal and also on a second test-mode control signal.

A memory in integrated circuit form organized as a matrix in rows and columns and comprising:

• at least one precharging and reading device associated with one or more rows, said device comprising
• a precharging element,
• a current-voltage converter and a read circuit,
• the selection of an associated row activating the precharging element and connecting the input of said converter to said row,
• the output of said converter being connected to the precharging element and to the input of the read circuit;
• and
• a test circuit connected to
• isolate the output of the converter from the precharging element and from the reading circuit,
• apply a test voltage to the output of the converter and measure a current at this output.

A method to measure the current of a cell of a memory in integrated circuit form comprising a device for the precharging and reading of said memory cell, said device comprising a precharging element, a current-voltage converter and a read circuit, said method comprising the steps of:

• selecting said cell;
• activating the precharging element;
• connecting the input of said converter to said row, the output of said converter being connected to the precharging element and to the input of the read circuit;
• applying a testing voltage to the output of said converter;
• and
• measuring the current therein, while the precharging element and the reading circuit are set in the inactive state.