US 5,675,538 AGranted

Non-volatile semiconductor memory device having a reference voltage applied to a sense line after data read out is complete

AssigneeSamsung Electronics Co., Ltd.

InventorsJong-Min Park, Young-Joon Choi

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Abstract

Disclosed is a memory device which includes a memory cell array having a plurality of bit lines arranged in parallel, a plurality of word lines electrically insulated and crossed with the bit lines, and a plurality of memory cells connected with corresponding bit lines. Each of the memory cells has at least one floating gate memory transistor. A reference voltage generator generates a reference voltage that is applied to a sense line which corresponds to a selected word line that is selected when data is read out. Further, the present invention advantageously provides a discharging transistor that discharges the reference voltage on the sense line selected when the reading operation is complete in order to prevent application of a voltage to the floating gate of the memory cell for a period of time which is longer than necessary. As a result, undesired changes in the threshold voltage are minimized.

Claims9

Dependent claims

A non-volatile memory device capable of preventing erroneous read out of data, said memory device comprising:

a memory cell array including:
a plurality of bit lines arranged in parallel,
a plurality of word lines electrically insulated from said plurality of bit lines,
a plurality of sense lines electrically insulated from said plurality of bit lines and said plurality of word lines, and
a plurality of memory cells, each memory cell connected to a corresponding bit line and including at least one memory transistor having a control gate connected with a corresponding sense line and a floating gate for storing electrical charge;
a reference voltage generating circuit that generates a reference voltage which is applied to a selected one of said sense lines selected when a data read out operation is performed on a selected memory cell;
and
a discharging circuit that discharges through a discharging path to a ground voltage level said reference voltage on said selected one of said sense lines when said data read out operation is complete, said discharging circuit including a discharging transistor having a gate controlled by a discharging signal and said discharging signal being generated by a pulse generator, said pulse generator also generating a sense amplifier activation signal and a latch signal.

5 more elements

A non-volatile memory device capable of preventing erroneous read out of data, said memory device comprising:

a memory cell array including:
a plurality of bit lines arranged in parallel,
a plurality of word lines electrically insulated from said plurality of bit lines,
a plurality of sense lines electrically insulated from said plurality of bit lines and said plurality of word lines, and
a plurality of memory cells, each memory cell connected to a corresponding bit line and including at least one memory transistor having a control gate connected with a corresponding sense line and a floating gate for storing electrical charge;
a control circuit for selecting one of said memory cells during a data read out operation, an associated one of said memory transistors being connected to a corresponding bit line during said data read out operation;
and
a voltage supplying circuit for providing a reference voltage to a selected one of said sense lines during a data read out operation, said voltage supplying circuit dropping said reference voltage on said selected sense line to a ground voltage when said data read out operation is complete;
wherein a selected one of said word lines remains activated for a period of time which is longer than said data read out operation.

6 more elements

Dependencies are inferred from the claim text.