Flash memory device

A flash memory device, comprising:

• a first switching means for supplying a latched program data signal to a first node according to a program data input signal;
• a second switching means for supplying a power supply voltage to a second node based on a program verification enable signal;
• a third switching means for supplying a drain voltage when programming to a third node based on a program enable-bar signal;
• a fourth switching means for supplying a ground potential to a fourth node based on said program enable-bar signal;
• a cross coupled latch circuit coupled between said third node and said fourth node, for latching said drain voltage or said power supply voltage in said first and second nodes based on the switching of said first, second, third and fourth switching means;
• a fifth switching means for supplying said drain voltage of said first node to a fifth node based on said program enable-bar signal;
• a column decoder for supplying said drain voltage via said fifth switching means to a selected memory cell based on column decoder signals;
• and
• a sixth switching means for supplying said power supply voltage to said fifth node according to said program verification enable signal.