Fast access memory array

A memory array including a plurality of memory cells arranged in rows and columns, comprising:

• a plurality of sense amplifiers located at the periphery of the subarray;
• a plurality of columns associated with the plurality of sense amplifiers respectively, each one of the plurality of columns including:
• a global bit line;
• a local bit line with a memory cell coupled thereto;
• and
• a switch coupled between the local bit line and the global bit line and configured to selectively move the global bit line in response to the contents of the memory cell during a read operation, wherein the switch is an MOS transistor having its drain coupled to the global bit line, its gate coupled to the local bit line, and its source coupled to a reference voltage.

A method of providing a memory array including a plurality of memory cells arranged in rows and columns, the method comprising:

• providing a plurality of columns, each one of the plurality of columns including:
• providing a global bit line;
• providing a local bit line with a memory cell coupled thereto;
• and
• providing an MOS switch having its drain coupled to the global bit line, its gate coupled to the local bit line, and its source coupled to a reference voltage and configured to selectively couple the local bit line and the global bit line in response to a column select signal.

A method of providing a memory array including a plurality of memory cells arranged in rows and columns, comprising the steps of:

• providing a plurality of sense amplifiers located at the periphery of the subarray;
• providing a plurality of columns associated with the plurality of sense amplifiers respectively, each one of the plurality of columns including:
• providing a global bit line;
• providing a local bit line with a memory cell coupled thereto;
• and
• providing a switch coupled between the local bit line and the global bit line and configured to selectively move the global bit line in response to the contents of the memory cell during a read operation, wherein the provided switch is an MOS transistor having its drain coupled to the global bit line, its gate coupled to the local bit line, and its source coupled to a reference voltage.

A method of operating a memory array having a plurality of columns, each one of the plurality of columns including a global bit line, a local bit line with a memory cell coupled thereto and a switch configured to selectively couple the local bit line and the global bit line in response to a column select signal, the method comprising the steps of:

• generating a column select signal in response to an output signal from a column decoder;
• activating a word line associated with the memory cell to substantially coincide with the step of generating the column select signal;
• selectively coupling the local bit line and the global bit line in response to a column select signal;
• and
• accessing the memory cell.