Current-mode parallel analog-to-digital converter

An integrated circuit chip, including an analog-to-digital converter comprising:

• a current splitter for splitting an analog input current I.sub.in into a plurality of substantially matched first current sources;
• a current generator that provides a plurality of second current sources, each second current source associated with a unique reference current that differs from that of any other second current source;
• a plurality of current regulators;
• and
• a plurality of conductive channels, each channel providing a summing node coupled to a respective first current source, a respective second current source, and a respective current regulator, wherein for each channel
• (a) if the respective first current source couples a first current to the channel that is larger than the reference current associated with the respective second current source, then the respective second current source couples the reference current associated therewith to the channel, the respective current regulator couples a difference current to the channel, the difference current representing a difference in current between the first current and the reference current associated with the respective second current source, thereby indicating a first logic state associated with the channel, and
• (b) if the respective first current source couples a first current to the channel that is smaller than the reference current associated with the respective second current source, then the respective current regulator couples essentially zero current to the channel, thereby forcing the respective second current source to couple approximately the first current to the channel and indicating a second logic state associated with the channel, and
• wherein the respective first current source has a substantially higher output impedance than the respective second current source.

An integrated circuit chip, including an analog-to-digital converter comprising:

• a current splitter for splitting an analog input current I.sub.in in the range of 0 to I.sub.max into a plurality of first current sources, each first current source for generating a substantially constant current of I.sub.in /2.sup.N and having a first output impedance when generating I.sub.in /2.sup.N ;
• a current generator for providing a plurality of second current sources, each second current source having an output impedance that is low relative to the first output impedance when generating currents in the range of I.sub.max /2.sup.2N to I.sub.max, each second current source capable of generating a unique reference current in the range of I.sub.max /2.sup.2N to I.sub.max, wherein each reference current differs from a closest reference current by I.sub.max /2.sup.2N ;
• a plurality of diodes;
• and
• a plurality of conductive channels, each channel providing a summing node coupled to a respective first current source, a respective second current source, and a respective diode, wherein one of the respective first and second current sources injects current into the channel, and the other of the respective first and second current sources draws current from the channel, wherein for each channel,
• (a) if the respective first current source couples a first current to the channel that is larger than the reference current for the respective second current source, then the respective second current source couples the reference current thereof to the channel, and the diode couples a difference current to the channel, the difference current representing a difference in current between the first current and the reference current for the respective second current source, thereby generating a first voltage at the channel representing a first logic level for the channel, and
• (b) if the respective first current source couples a first current to the channel that is smaller than the reference current for the respective second current source, then the diode couples essentially zero current to the channel, thereby adjusting the respective second current source to couple the first current to the channel and generating a second voltage at the channel representing a second logic level at the channel.

An integrated circuit chip, including an analog-to-digital converter comprising:

• a current splitter for splitting an analog input current I.sub.in, in the range of approximately 0 to I.sub.max, into 2.sup.N first current sources, wherein each first current source provides a substantially constant current of approximately I.sub.in /2.sup.N ;
• a current generator comprising 2.sup.N second current sources, wherein each second current source is capable of providing (i) a substantially constant reference current, different than the reference current of any other second current source by a constant quantization level, and (ii) approximately I.sub.in /2.sup.N ;
• 2.sup.N current regulators;
• 2.sup.N output nodes for providing a 2.sup.N element digital code associated with I.sub.in ;
• and
• 2.sup.N conductive channels, each channel coupled between a respective first current source and a respective second current source for unidirectional current flow therebetween, each channel also coupled to a respective current regulator and a respective output node, wherein for each channel,
• (a) if approximately I.sub.in /2.sup.N coupled by the respective first current source to the channel is greater than the reference current for the respective second current source, then the respective second current source couples approximately the reference current thereof to the channel, the respective current regulator couples to the channel a difference current of approximately a difference between I.sub.in /2.sup.N and the reference current for the respective second current source, and a first logic state is indicated at the respective output node, and
• (b) if approximately I.sub.in /2.sup.N coupled by the respective first current source current to the channel is less than approximately the reference current for the respective second current source then, the respective second current source adjusts to couple approximately I.sub.in /2.sup.N to the channel, the respective current regulator couples approximately zero current to the channel, and a second logic state is indicated at the respective output node, and
• wherein, for each channel, the respective first current source includes a first transistor, the respective second current source includes a second transistor, and the first transistor has a substantially higher output impedance than the second transistor.

A method of performing analog-to-digital conversion, including:

• providing a plurality of first current sources each having an impedance;
• providing a plurality of second current sources, each second current source having an impedance that is low relative to the impedance of a corresponding one of the first current sources and being associated with a unique reference current that differs from that of any other second current source;
• providing a plurality of current regulators;
• providing a plurality of conductive channels, each channel coupled to a respective first current source, a respective second current source, and a respective current regulator, such that one of the respective first and second current sources injects current into the channel and the other of the respective first and second current sources draws current from the channel;
• coupling an analog input current to the first current sources such that a portion of the analog input current is coupled to and controls each first current source;
• generating a first voltage at each channel where the respective first current source couples a larger current to the channel than the reference current associated with the respective second current source, including the respective current regulator coupling a difference current to the channel and the respective second current source coupling the reference current associated therewith to the channel;
• and
• generating a second voltage at each channel where the respective first current source couples a smaller current to the channel than the reference current associated with the respective second current source, including the respective current regulator not coupling a difference current to the channel and the respective second current source coupling a current to the channel approximately equal to the current coupled by the respective first current source to the channel.

In an integrated circuit chip including a current splitter for splitting an analog input current into a plurality of substantially matched first current sources, a plurality of second current sources with each second current source associated with a unique reference current, a plurality of current regulators, and a plurality of conductive channels with each channel coupled to (1) a respective first current source, (2) a respective second current source with substantially lower output impedance than the respective first current source, and (3) a respective current regulator, a method of performing analog-to-digital conversion comprising the steps of:

• applying the analog input current to the current splitter;
• providing a first voltage at each channel where current coupled to the channel by the respective first current source is larger than the reference current associated with the respective second current source by operating the respective current regulator to couple a difference current to the channel thereby allowing the respective second current source to couple the reference current associated therewith to the channel;
• and
• providing a second voltage at each channel where current coupled to the channel by the respective first current source is equivalent to or smaller than the reference current for the respective second current source by operating the respective current regulator to couple essentially zero current to the channel thereby forcing the respective second current source to couple to the channel essentially the current coupled to the channel by the respective first current source;
• thereby providing a digital signal that includes logic states corresponding in one-to-one relationship to the channels wherein each channel at the first voltage indicates a first logic state and each channel at the second voltage indicates a second logic state.