Plural-step chunk-at-a-time decoder for variable-length codes of Huffman type

A decoder for variable-length codewords of Huffman type supplied in a codestream having data segments in which each successive codeword comprises a pointer code segment with leading ONEs and a final ZERO followed by a target code segment, said decoder comprising:

• a selector for selecting successive uniform-bit-length portions of said codestream as a selector output signal, selection being in response to a modular count of the bits of a data segment within said codestream, each said uniform-bit-length portion being at least as long as the longest target code segment in any said codeword;
• an AND gate chain for complementing non-leading ONEs in each uniform-bit-length portion of the codestream selected by said selector, to generate a respective unary signal;
• adder circuitry for summing the bits of each said unary signal to generate a respective sum signal;
• a NOR gate responsive to the bits of the current one said sum signals, for detecting when the current one said sum signals is arithmetic zero to generate an indication of a final step in decoding a code word;
• a first accumulator for accumulating each said respective sum generated by said adder circuitry to generate a first accumulated output signal, said first accumulated output signal being reset to zero arithmetic value responsive to said first accumulator having a first accumulator reset signal applied thereto;
• first memory addressed by said first accumulated output signal and selected bits of said selector output signal, for storing look-up tables of decoder output signal;
• second memory for indicating the bit-lengths of just the target code portions of the complete Huffman codes that during the final steps of decoding variable-length code words access decoder output signals stored in said first memory;
• a two-input, single-output multiplexer receiving said respective sums generated by said adder circuitry as its first input signal, receiving said binary numbers read from said second memory as its second input signal, and selecting one of its first and second input signals as its output signal responsive to a control signal;
• a second accumulator for accumulating output signal from said multiplexer to generate a second accumulated output signal that controls the selecting by said selector, said second accumulated output signal being reset to zero arithmetic value responsive to said second accumulator having a second accumulator reset signal applied thereto;
• an output data latch for temporarily storing read-out from said first memory in response to a latching signal;
• and
• decoding control circuitry for generating said latching signal during each final step in decoding a code word as signaled by said NOR gate for detecting that the current one said sum signals is arithmetic zero, for generating said first accumulator reset signal at the beginning of each data segment and after each final step in decoding a code word as signaled by said NOR gate for detecting that the current one said sum signals is arithmetic zero, and for generating said second accumulator reset signal at the beginning of each data segment.

A decoder for variable-length codewords of Huffman type supplied in a codestream having data segments in which each successive codeword comprises a pointer code segment with leading ZEROs and a final ONE followed by a target code segment, said decoder comprising:

• a selector for selecting successive uniform-bit-length portions of said codestream as a selector output signal, selection being in response to a modular count of the bits of a data segment within said codestream, each said uniform-bit-length portion being at least as long as the longest target code segment in any said codeword;
• circuitry for bit-complementing each uniform-bit-length portion of the codestream selected by said selector, and
• an AND gate chain for complementing non-leading ONEs in the resulting signal, to generate a respective unary signal;
• adder circuitry for summing the bits of each said unary signal to generate a respective sum signal;
• a NOR gate responsive to the bits of the current one said sum signals, for detecting when the current one said sum signals is arithmetic zero to generate an indication of a final step in decoding a code word;
• a first accumulator for accumulating each said respective sum generated by said adder circuitry to generate a first accumulated output signal, said first accumulated output signal being reset to zero arithmetic value responsive to said first accumulator having a first accumulator reset signal applied thereto;
• first memory addressed by said first accumulated output signal and selected bits of said selector output signal, for storing look-up tables of decoder output signal;
• second memory for indicating the bit-lengths of just the target code portions of the complete Huffman codes that during the final steps of decoding variable-length code words access decoder output signals stored in said first memory;
• a two-input, single-output multiplexer receiving said respective sums generated by said adder circuitry as its first input signal, receiving said binary numbers read from said second memory as its second input signal, and selecting one of its first and second input signals as its output signal responsive to a control signal;
• a second accumulator for accumulating output signal from said multiplexer to generate a second accumulated output signal that controls the selecting by said selector, said second accumulated output signal being reset to zero arithmetic value responsive to said second accumulator having a second accumulator reset signal applied thereto;
• an output data latch for temporarily storing read-out from said first memory in response to a latching signal;
• and
• decoding control circuitry for generating said latching signal during each final step in decoding a code word as signaled by said NOR gate for detecting that the current one said sum signals is arithmetic zero, for generating said first accumulator reset signal at the beginning of each data segment and after each final step in decoding a code word as signaled by said NOR gate for detecting that the current one said sum signals is arithmetic zero, and for generating said second accumulator reset signal at the beginning of each data segment.