Phase-lock loop with reduced acquistion time

#The present invention relates to phase-lock loop circuits and, in particular, to an improved charge pump circuit for use in a phase-lock loop circuit such that the phase-lock loop circuit which includes the improved charge pump circuit has a decreased loop acquisition time when the loop reacquires "lock" in response to phase/frequency changes.

#Phase-lock loop circuits ("PLL's") are well-known. For example, one common application for a PLL is a frequency synthesizer. A frequency synthesizer generates an output signal whose frequency can be one of various fixed multiples (e.g., N) of a given reference signal. Thus, the PLL accomplishes frequency multiplication based upon a fixed reference input. FIG. 1 is a block diagram illustrating a conventional PLL 10 used for frequency multiplication. A reference signal L, having frequency f.sub.L and phase .phi..sub.L is generated by a reference signal generator 12. Meanwhile, a voltage controlled oscillator 14 generates an output signal OUT, having frequency f.sub.out and phase .phi..sub.out, in response to a control voltage V.sub.2 provided at the input of VCO 14. Once the PLL has "locked on" to the reference signal L, the frequency f.sub.out is N times f.sub.L.

#To "close the loop", the output signal OUT is provided to a "divide by N" circuit 16, which provides an output signal COMP, having a frequency f.sub.COMP such that f.sub.COMP is f.sub.OUT divided by N. The signal COMP and the signal L are provided to a phase/frequency detector 18. The phase/frequency detector 18 is of the type which provides output voltage error pulses whose duration represents the magnitude of the time difference between .phi..sub.L and .phi..sub.COMP and whose polarity represents the polarity of the time difference between .phi..sub.L and .phi..sub.COMP.

#FIG. 1 illustrates, in block form, a phase lock loop circuit (PLL) 10.

#FIG. 2 schematically illustrates a conventional arrangement of the charge pump circuit and the loop filter circuit (designated by the reference numerals 20 and 22, respectively) of the PLL 10.

#FIG. 3 schematically illustrates an arrangement of the charge pump circuit and the loop filter in accordance with an embodiment of the present invention (designated by the reference numerals 120 and 122, respectively).

#FIG. 3 schematically illustrates an arrangement of the charge pump circuit 120 and the loop filter 122 in accordance with an embodiment of the present invention. Where the components are the same as those of FIG. 2, they are given the same reference designations. For example, the resistor R2 and capacitor C1 shown in FIG. 3 are identical to the resistor R2 and capacitor C1 shown in FIG. 2.

#As shown in FIG. 3, the charge pump circuit 120 includes an additional current source I.sub.i (i.e., in addition to the current source I.sub.p) which also provides current pulses I.sub.i in response to the output voltage pulses provided from the phase detector 18. The current source I.sub.i is selectively connected, via a switch 124, to an internal node 126 of the loop filter 122. The internal node 126 is between the resistor R2 and the capacitor C1. In a preferred method of operating the charge pump circuit 120, the switch 124 is opened and closed in response to an "acquire" signal being deasserted and asserted, respectively. The state of the acquire signal is controlled, for example, by a microprocessor or a timing circuit (not shown). When the acquire signal is not asserted (and the switch 124 is open), the charge pump circuit 120 and the loop filter 122 operate identically to the conventional charge pump circuit 20 and the conventional loop filter 22 shown in FIG. 2. However, when the acquire signal is asserted (and the switch 124 is closed), the current source I.sub.i provides additional charge to the capacitor C1 to bring the voltage V2 more quickly to the voltage level needed for phase frequency lock acquisition (i.e., the voltage controlling the VCO operating frequency that enables the loop to lock up/down to the frequency of the reference signal provided by the reference signal generator 12).

#FIGS. 4A through 4H are a timing diagram which is helpful to understand the operation of the PLL circuit 10 having the arrangement of the charge pump circuit 120 and the loop filter 122 shown in FIG. 3. As shown in FIG. 4A, the reference signal L provided from the reference signal generator 12 initially (i.e., during time period T1) has a first frequency. During the time period T1, the acquire signal is not asserted (FIG. 4E) and the current source I.sub.p is providing only brief "correction" pulses (FIG. 4C) to keep the loop filter voltage V2' (FIG. 4G) at a first level so that the signal COMP output from the divide-by-N circuit 16 has a frequency equal to the frequency of the reference signal L. During the time period T1, the current source I.sub.i does not provide any current to the internal node 126 of the loop filter 122.