Frequency lock indicator for FPLL demodulated signal having a pilot

Abstract

A biphase stable FPLL includes a polarity determination circuit that ascertains the lockup phase of the FPLL based upon the polarity of the pilot in the digital signal. A frequency lock indicator circuit determines from the recovered pilot when frequency lock has occurred and the polarity determination circuit is responsive thereto for inverting the phase of the incoming signal (or alternatively, of the outgoing signal) as determined in order to supply an output signal of predetermined polarity. The frequency lock indicator consists of a zero crossings detector and a latch that is sampled for a time period. The zero crossings detector is a delay and an exclusive OR gate. An optional confidence counter may be used with the latch to determine when frequency lock has occurred to provide the lock indicator signal.

Dependencies are inferred from the claim text.