Voltage stepup circuit for integrated semiconductor circuits

A voltage stepup circuit, comprising:

• a plurality of stepup circuit units connected in series between an input voltage node receiving a supply voltage and an output voltage node, each stepup circuit unit comprising a first MOS and a second MOS transistor connected in series, each first and second MOS transistor having a drain and a gate connected together, each second MOS transistor having a source connected to the drain and gate of a first MOS transistor of a next series-connected stepup circuit unit, the source of the second MOS transistor of a last one of said plurality of stepup circuit units being connected to the output voltage node, and the drain and the gate of the first MOS-transistor of a first one of said plurality of stepup circuit units being connected to the input voltage node;
• a plurality of first stepup capacitors respectively connected between the drain and gate of the first MOS transistors of said plurality of stepup circuit units and a first clock signal supply node;
• a plurality of second stepup capacitors respectively connected between the drain and gate of the second MOS transistors of said plurality of stepup circuit units and a second clock signal supply node;
• first clock amplitude control circuit means for receiving a first clock signal, and for supplying a first amplitude-limited clock signal amplitude-limited to a predetermined level regardless of variations in the level of the supply voltage to the first clock signal supply node;
• and
• second clock amplitude control circuit means for receiving a second clock signal, and for supplying second amplitude-limited clock signal amplitude-limited to a predetermined level regardless of variations in the level of the supply voltage to the second clock signal supply node, said second amplitude-limited clock signal having a pulse width which does not overlap in time with that of the first amplitude-limited clock signal.