Power level sensing for mixed voltage chip design

A voltage level sensing circuit coupled between a first voltage source of a first magnitude, a second voltage source of a second magnitude, and a ground reference point to detect that the first magnitude is equal to the second magnitude, comprising:

• a) a threshold shifting means comprising an input terminal connected to the first voltage source, an output terminal, and a level shifting circuit connected between the input terminal and the output terminal to shift the first magnitude of the first voltage source to a third magnitude and place said third magnitude at the output terminal;
• b) a level sensor means comprising a sensor input terminal connected to the output terminal of the threshold shifting means, a sensor output terminal, a feedback leakage control terminal, and a Schmitt trigger circuit connected between the sensor input terminal, the sensor output terminal, and the leakage control terminal, wherein the sensor output has a sensor signal having a first level if the magnitude of the first voltage source is greater than a threshold voltage level and a second level if the first voltage source is less than the threshold voltage level;
• c) a first flip-flop circuit comprising a data input terminal connected to the sensor output terminal, a clock input terminal, a reset terminal, a data output terminal a detected result terminal connected to the data output terminal to transfer a detected result signal to external circuitry, and a bistable multivibrator means connected to the data input terminal, the clock input terminal, the reset terminal and the data output terminal;
• d) a second flip-flop circuit comprising a data input terminal connected to the second voltage source, a clock input terminal, a reset terminal, a data output terminal connected to the feedback leakage control terminal, and a bistable multivibrator means connected to the data input terminal, the clock input terminal, the reset terminal and the data output terminal;
• e) a system reset terminal coupled to the reset terminals of the first and second flip flops to provide a power-on-reset signal to said voltage level sensing circuit, wherein the power-on-reset signal changes from a first logic level to a second logic level at a period of time after the first and second voltage sources are activated and while the power-on-reset signal is at the first level, the detected result signal assumes a first output level;
• and
• f) a buffer circuit connected between the system reset terminal and the clock input terminals of the first and second flip-flops circuits to delay the power-on-reset signal.