Signal amplifying device
AssigneeSharp Kabushiki Kaisha
InventorMasahiro Kawate
Life of this patent
Estimating the term…
Abstract
A signal amplifying device including a sense amplifier for receiving first and second signals having respective logical levels from memory cells, and for, when activated in response to an actuating signal, outputting third and fourth signals having respective logical levels in accordance with the logical levels of the first and second signals; and output means for receiving the actuating signal, and the third and fourth signals, and for outputting an output signal having a logical level in accordance with a combination of the actuating signal and the logical levels of the third and fourth signals.
Claims6
A signal amplifying device comprising:
- a sense amplifier for receiving first and second signals having respective logical levels from memory means, and for, when activated in response to an active signal, outputting third and fourth signals having respective logical levels in accordance with the logical levels of the first and second signals;
- and
- output means comprising an output terminal, first means and first, second, third and fourth transistors, each of said first, second, third and fourth transistors having a drain, a source and a gate, for outputting an output signal having one of a first level and a second level based on said third and fourth signals and said active signal;
- wherein said source of said first transistor is connected to said drain of said second transistor, said source of said second transistor is connected to said output terminal and said drain of said third transistor, and said source of said third transistor is connected to said drain of said fourth transistor;
- said first means receives said active signal, and said third and fourth signals, and generates fifth and sixth signals having one of a first level and a second level based on said active signal, said third signal and said fourth signal;
- said gates of said first and third transistors receive said fifth signal and said gates of said second and fourth transistors receive said sixth signal;
- said first and fourth transistors are turned off in order to set said output terminal of said output means to a high-impedance state when said fifth signal is at one level and said sixth signal is at the other level of said first and second levels;
- said output signal is output from said output terminal when a level of said fifth signal is the same as a level of said sixth signal;
- a level of said output signal is different from said level of said fifth signal;
- and
- said output signal has either a high logical level or a low logical level.
A signal amplifying device:
- a sense amplifier for receiving first and second signals having respective logical levels from memory means, and for, when activated in response to an active signal, outputting third and fourth signals having respective logical levels in accordance with the logical levels of the first and second signals;
- and
- output means for receiving the active signal, and said third and fourth signals, said output means setting an output of said output means to a high-impedance state when said sense amplifier is not activated and for outputting an output signal having a logical level in accordance with a combination of said active signal and the logical levels of said third and fourth signals
- wherein said output means comprises:
- a first inverter for receiving said third signal, inverting said logical level of said third signal when said level of said third signal is larger than a threshold level, and outputting a first inverted signal;
- a nand element for receiving said first inverted signal and said active signal, and outputting a fifth signal having a logical level in accordance with a combination of said first inverted signal and said active signal;
- a second inverter for receiving said active signal, inverting said logical level of said active signal when said level of said active signal is larger than a threshold level, and outputting a second inverted signal;
- an element for receiving said fourth signal, and outputting said fourth signal when said level of said fourth signal is larger than a threshold level;
- and
- a nor element for receiving said second inverted signal and said fourth signal from said element, and outputting a sixth signal having a logical level in accordance with a combination of said second inverted signal and said fourth signal from said element.
Dependencies are inferred from the claim text.