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US 5,675,264 AGranted
Phase differential circuit having high synchronicity
AssigneeNEC Corporation
InventorMakoto Yoshida
Life of this patent
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Abstract
A differential circuit configuration for generating an inverted signal and a non-inverted signal of an original signal is presented. The waveforms of the output signals are highly synchronous and precise owing to the circuit design which provides matched gate-to-source voltage vs drain-to-source current to produce output trace matching in the output voltage traces of a pair of pull-up transistors with a pair of pull-down transistors. The circuit configuration does not require adjustable capacitors or driving circuits, and is therefore suitable for use in advanced compact devices.
Claims5
A phase differential circuit comprising:
- a first inverter circuit for inverting an input signal;
- a second inverter circuit for non-inverting said input signal, wherein said second inverter includes a first output transistor and a second output transistor;
- said first output transistor connected between a first power supply terminal and a first output terminal having a gate terminal connected to a second output terminal of said first inverter;
- said second output transistor connected between a second power supply terminal and said first output terminal having a gate terminal connected to a third output terminal of said first inverter;
- a first transfer means connected between a fourth output terminal of said first inverter and a second output terminal for transferring a signal from said fourth output terminal of said first inverter to said second output terminal;
- a second transfer means connected between said fourth output terminal of said first inverter and said third output terminal for transferring said signal from said fourth output terminal of said first inverter to said third output terminal;
- wherein the current driving capacity of said first output transistor and the current driving capacity of said first transfer means are matched, and the current driving capacity of said second output transistor and the current driving capacity of said second transfer means are matched.
4 more elements
A circuit for generating an inverted digital signal and a non-inverted signal, each signal having a synchronicity to an original digital signal, said circuit comprising:
- a first N-MOS transistor for pull-down of said non-inverted signal output of said original input signal;
- a first P-MOS transistor for pull-up of said inverted output signal of said original input signal;
- a second P-MOS transistor for driving said first P-MOS transistor;
- and
- a second N-MOS transistor for potential control of said first N-MOS transistor;
- wherein said first N-MOS transistor has a source terminal at a ground potential and a drain terminal connected to an output terminal of said non-inverted signal,
- said first P-MOS transistor has a gate terminal at a ground potential and a drain terminal connected to an output terminal of said inverted signal;
- and
- a gate terminal of said first N-MOS transistor, a source terminal of said first P-MOS transistor, a drain terminal of said second P-MOS transistor and a drain terminal of said second N-MOS transistor are all connected to a common point such that push-pull signals are generated in a complimentary circuit configuration.
6 more elements
A phase differential circuit comprising:
- a first P channel MOS transistor connected between a first power supply terminal and a first node having a gate terminal connected to an input terminal;
- a second P channel MOS transistor connected between said first power supply terminal and a second node having a gate terminal connected to said input terminal;
- a third P channel MOS transistor connected between said first power supply terminal and a first output terminal having a gate terminal connected to said second node;
- a first N channel MOS transistor connected between a second power supply terminal and said second node having a gate terminal connected to said input terminal;
- a second N channel MOS transistor connected between said second power supply terminal and said first node having a gate terminal connected to said input terminal;
- a third N channel MOS transistor connected between said second power supply terminal and said first output terminal having a gate terminal connected to said first node;
- a first transfer means connected between said first node and a second output terminal;
- a second transfer means connected between said second node and said second output terminal;
- wherein the current driving capacity of said first transfer means and the current driving capacity of said third N channel MOS transistor are matched;
- and
- wherein the current driving capacity of said second transfer means the current driving capacity of said third P channel MOS transistor are matched.
8 more elements
Dependencies are inferred from the claim text.