US 5,675,260 AGranted

Electrostatic discharge test structure system and method

AssigneeLSI Logic Corporation

InventorRosario J. Consiglio

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Abstract

System and method for optimizing the structure of a transistor to withstand electrostatic discharge by quantitatively evaluating the amount of electrostatic discharge that integrated circuit field effect transistors may endure before material damage results thereto. The system and method utilizes a plurality of test devices, each having certain differences in structure, which are fabricated onto a common integrated circuit substrate for contemporaneous testing of each device under controlled quantitative conditions. The test results may be organized into a "matrix experiment". A matrix experiment is a set of experiments where the settings or values of several product or process parameters to be studied are changed from one experiment to another. An orthogonal matrix array may be utilized to enhance the reliability of the data analysis, and may effectively reduce the number of experiments necessary to establish a reliable conclusion from the limited number of tests performed.

Claims6

Dependent claims

An apparatus having an arrangement of different shaped structures of metal-oxide semiconductor field effect transistors on a semiconductor integrated circuit die, whereby design parameters are determined for an optimal shape of the field effect transistor structure, wherein the optimal shape of the field effect transistor structure is determined by the transistor structure having the best tolerance to electrostatic discharge without substantially degrading electrical circuit performance of the field effect transistors, said apparatus comprising:

a semiconductor integrated circuit die having a plurality of metal-oxide semiconductor field effect transistors, each of the plurality of metal-oxide semiconductor field effect transistors being individually testable, each of the plurality of metal-oxide semiconductor field effect transistors having a unique combination of element shape parameters different from the other metal-oxide semiconductor field effect transistors, and each of the plurality of metal-oxide semiconductor field effect transistors has source, gate and drain elements;
a guard ring element surrounding the source, gate and drain elements of each of the plurality of metal-oxide semiconductor field effect transistors;
and
a plurality of contact pads on the semiconductor integrated circuit die, the plurality of contact pads connected to the source, gate, drain and guard ring elements of the plurality of metal-oxide semiconductor field effect transistors, wherein the plurality of contact pads allow connection of the plurality of metal-oxide semiconductor field effect transistors to an electrostatic discharge test device.

1 more element

An apparatus for testing different shaped structures of metal-oxide semiconductor field effect transistors on a semiconductor integrated circuit die, whereby design parameters are determined for an optimal shape of the field effect transistor structure, wherein the optimal shape of the field effect transistor structure is determined by the transistor structure having the best tolerance to electrostatic discharge without substantially degrading electrical circuit performance of the field effect transistors, said apparatus comprising:

a semiconductor integrated circuit die having a plurality of metal-oxide semiconductor field effect transistors, each of the plurality of metal-oxide semiconductor field effect transistors being individually testable and each of the plurality of metal-oxide semiconductor field effect transistors having a unique combination of dement shape parameters different from the other metal-oxide semiconductor field effect transistors;
a plurality of contact pads on the semiconductor integrated circuit die, each of the plurality of contact pads connected to respective elements of the plurality of metal-oxide semiconductor field effect transistors;
means for measuring leakage current of each of the plurality of metal-oxide semiconductor field effect transistors by connecting the leakage current measuring means to the plurality of contact pads connected to the respective elements of the plurality of metal-oxide semiconductor field effect transistors;
means for pulsing each of the plurality of metal-oxide semiconductor field effect transistors with a pulse having a controllable amplitude and time duration by connecting the pulsing means to the plurality of contact pads connected to the respective elements of the plurality of metal-oxide semiconductor field effect transistors;
and
means for measuring current and voltage values for each of the plurality of metal-oxide semiconductor field effect transistors during the pulse.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/751,567Filed 18 Nov 1996 · continuation
Priority: 4 Mar 1993
Granted: 7 Oct 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G01R 31/002
Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing: where the device…
G01R 31/2623
For testing field effect transistors, i.e. FET's: for measuring break-down voltage therefor
G01R 31/275
Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements: for…
G01R
Measuring electric variables