Universal test die and method for fine pad pitch designs

Abstract

A universal semiconductor interconnect test structure and method for using the test structure is provided for detecting the presence of electrical open or short circuits within the test package. In one embodiment, the test structure comprises a layer of electrically non-conductive substrate and a bonding layer of electrically conductive material over the substrate layer. In a second embodiment, the universal test die comprises a layer of electrically non-conductive substrate and a pattern of electrically conductive material over the substrate layer, wherein the pattern forms a continuous array of individual bonding areas, each of the bonding areas being electrically isolated from adjacent bonding areas by a gap, and wherein the effective pitch of the bonding areas is not more than 25 microns. The universal test die of the present invention is suitable for developing wire bond and mold processes for all pad pitches, all pad layout designs, all package types, and all pin counts. The test die of the present invention greatly accelerates fine pitch development and avoids the burden of multiple test die inventory control. Additionally, the test die of the present invention simplifies wire bond programming and test program development.

Dependencies are inferred from the claim text.