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AssigneeHitachi, Ltd.
InventorsMasafumi Miyamoto, Tatsuya Ishii
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A MIS device comprising a pair of first doped layers of a second conductivity type forming source/drain regions in a semiconductor base structure of a first conductivity type, and a gate electrode formed in a region between the first doped layers of the second conductivity type on a gate insulating film formed on the semiconductor base structure having a three-layer structure consisting of a second doped layer of the first conductivity type, a third doped layer of the second conductivity type and a fourth doped layer of the first conductivity type having an impurity concentration higher than that of the semiconductor base structure, which are formed in that order in the direction of depth from the surface of a channel region extending between the source/drain regions, the thickness of the third doped layer is determined so that the third doped layer is depleted by the respective built-in potentials of pn junctions formed by the second doped layer and the third doped layer and by the fourth doped layer and the third doped layer, respectively. Even when the MIS device of this structure is miniaturized, the subthreshold swing can be reduced to a value small enough to enable the lowering of the threshold voltage, the electric field intensity in the interface of the gate insulating film is reduced to enhance the carrier mobility and hence the MIS device is suitable for low-voltage operation.
In a MIS device comprising a pair of first doped layers of a second conductivity type forming source/drain regions in a semiconductor base structure of a first conductivity type, and a gate electrode formed in a region between the first doped layers of the second conductivity type on a gate insulating film formed on the semiconductor base structure, the improvement comprising:
In a MIS transistor device comprising a pair of first doped layers of a second conductivity type forming source/drain regions at a main surface in a semiconductor body of a first conductivity type, and a gate electrode formed, through a gate insulating film, on a region above a base layer of said semiconductor body between the first doped layers of the second conductivity type, the improvement comprising:
A MIS device constituted by at least one pair of complementary MIS transistors formed in respectively separate regions of a common semiconductor body, wherein each transistor has upper, first level doped layers for forming source/drain regions at a main surface of said semiconductor body, and a gate electrode formed, through a gate insulating film, on a region above a base layer in a corresponding portion of said semiconductor body between the source/drain regions of that MISFET, the improvement comprising:
Dependencies are inferred from the claim text.