Unsymmetrical MOS device having a gate insulator area offset from the source and drain areas, and ESD protection circuit including such a MOS device

An ESD protection circuit, comprising:

• an I/O pad for sending in and out an electric signal;
• a terminal for supplying a prescribed potential;
• a first NchMOSFET having a drain connected to the I/O pad and a source and a gate both connected to the terminal;
• and
• a second NchMOSFET having a drain connected to the I/O pad and a source and a gate both connected to the terminal,
• wherein the first NchMOSFET and the second NchMOSFET each include:
• a semiconductor layer of a p-type having a surface having a first area and a second area which is offset from the first area;
• a gate insulator layer located on the first area of the surface of the semiconductor layer;
• a gate electrode located on the gate insulator layer;
• and
• a source region of an n-type and a drain region of an n-type each located in the semiconductor layer below the second area of the surface,
• wherein the second NchMOSFET includes an impurity diffusion region of an n-type between an area immediately beneath the first area of the surface and the source region, and the electric resistance of an area between the first area of the surface and the surface of the source region is smaller than the electric resistance of an area between the first area of the surface and the surface of the drain region in the second NchMOSFET.