Enhancement-type semiconductor having reduced leakage current
AssigneeNippondenso Co., Ltd.
InventorsHiroyuki Yamane, Yasushi Higuchi, Mitsutaka Katada, Noriyuki Iwamori, Tsutomu Kawaguchi, Takeshi Kuzuhara
Life of this patent
Estimating the term…
Loading patent…
AssigneeNippondenso Co., Ltd.
InventorsHiroyuki Yamane, Yasushi Higuchi, Mitsutaka Katada, Noriyuki Iwamori, Tsutomu Kawaguchi, Takeshi Kuzuhara
Estimating the term…
A semiconductor device having an enhancement-type MOS structure which can prevent large leakage current is disclosed. A high-concentration region for threshold-value regulation use formed in a channel region below a gate electrode in an enhancement-type transistor is caused to be contiguous with a source region and not contiguous with a drain region. Herein, the distance between the high-concentration region and the drain region is set so as to preclude the depletion layer extending from the drain region side from reaching the high-concentration region. Therefore, the electrical field in the depletion layer does not become the critical field which causes avalanche or Zener breakdown, and so leakage current can be caused to be reduced.
A semiconductor device comprising:
A semi-conductor device comprising:
Dependencies are inferred from the claim text.