Stable SRAM cell using low backgate biased threshold voltage select transistors

Abstract

The present invention provides a more stable SRAM cell by reducing the backgate biased threshold voltage of the SRAM's select transistor. In some embodiments, masking layers are used during dopant implantation of the select transistors to minimize the net dopant concentration in the select transistor's channel region. Minimizing this net dopant concentration lowers the backgate biased threshold voltage of the select transistor without any reduction in its on-resistance. Another embodiment may be used to achieve increased stability for SRAM cells formed with CMOS technology. The masking layers used to form N-type and P-type well regions are overlapped such that a third well formed intermediate the N-type and P-type wells has a dopant concentration equal to the net concentrations of the respective N-type and P-type wells. This third well, therefore, may be used as discussed above to achieve a lower backgate biased threshold voltage. Yet another embodiment is provided in which a lower backgate biased threshold voltage is achieved by reducing a portion of the length of the channel region while the lengths of other portions of the channel are unaltered.

Dependencies are inferred from the claim text.