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AssigneeInternational Business Machines Corporation
InventorsTimothy A. Brunner, Louis L. Hsu, Jack A. Mandelman, Li-Kong Wang
Estimating the term…
A high performance transistor includes mesa structures in a conduction region, favoring corner conduction, together with lightly doped mesa structures and mid-gap gate material also favoring operation in a fully depleted mode. Mesa structures are formed at sub-lithographic size and pitch as recesses or by epitaxial growth together with exposure of a resist by an interference pattern generation with illuminating radiation and multiple exposures using a mask shifted by a sub-lithographic distance. For an NFET, conduction electron and hole distribution profiles in the mesa structures and gate capacitance are adjusted with dielectric thickness, including deposition of oxide from a liquid solution at room temperature. Transconductance may be altered by change of the aspect ratio of the mesa structures. Lightly doped drain structures are also formed at sub-lithographic sizes by self-aligned processes.
A field effect transistor having a conduction region including a plurality of mesa structures, said mesa structures being formed at a pitch of less than one-half micron and a width of less than one-quarter micron by etching and doped to an impurity concentration to operate in a fully depleted mode.
A method of making a field effect transistor including the steps of
A semiconductor wafer having a region of a surface patterned with a plurality of elongated features which have a width less than or equal to one-quarter micron and a pitch less than or equal to one-half micron.
A method of making a semiconductor wafer including the steps of
A method of making a semiconductor wafer including the steps of
Dependencies are inferred from the claim text.