Packing valid micro operations received from a parallel decoder into adjacent locations of an output queue

A system for queuing micro-operations supplied from a macroinstruction decoder in a processor, each micro-operation having a valid bit associated therewith, the state of the valid bit indicating whether the respective micro-operation is valid or invalid, the system comprising:

• a plurality of selectors, each coupled to receive a plurality of micro-operations from the decoder, and operable to output a selected micro-operation;
• a memory circuit comprising a plurality of entries in which to maintain a queue of micro-operations, a target entry of the memory being designated as the next available location, each entry of the memory circuit being coupled to receive a selected micro-operation from a corresponding selector;
• and
• control circuitry configured to identify:
• a set of valid micro-operations indicated to be valid by the states of the respective valid bits;
• and
• the target entry of the memory circuit;
• and to operate the selectors to output the set of valid micro-operations:
• from a set of adjacent selectors, so as to pack the set of valid micro-operations;
• and
• so that the first micro-operation of the set of valid micro-operations is outputted from the selector corresponding to the target entry of the memory circuit.

A method of propagating micro-operations from a decoder of a processor to a queue maintained within a memory circuit, each micro-operation having a valid bit associated therewith, the state of the valid bit indicating whether the respective micro-operation is valid or invalid, the memory circuit comprising a plurality of entries in which to maintain the queue and having a target entry designated as the next available location, the method comprising the steps of:

• issuing a plurality of micro-operations from the decoder;
• examining the valid bit associated with each of the plurality of micro-operations to identify a set of valid micro-operations;
• packing the set of valid micro-operations by propagating the set of valid micro-operations to a set of consecutive entries in the memory circuit;
• identifying the target entry of the memory circuit;
• and
• aligning the set of valid operations by presenting a first micro-operation of the set of valid micro-operations to the target entry of memory circuit.