System for automatic generating instruction string to verify pipeline operations of a processor by inputting specification information having time for the processor to access hardware resources

An automatic instruction string generating method for verifying operations of a pipeline control mechanism of a processor, comprising the steps of:

• inputting specification information about a pipeline process of an instruction to be executed by the processor, the specification information including time for the processor to access hardware resources for the instruction;
• listing, according to the specification information, states in which hazards are caused between a last started instruction and an instruction preceding the last started instruction by execution of the last started instruction after the pipeline process has processed a pipeline of the processor without a stop, the state including information on a series of instructions in time order that causes the hazards;
• and
• generating an instruction string corresponding to each of the states listed by said listing step.

An automatic instruction string generating method for verifying operations of a pipeline control mechanism of a processor, comprising the steps of:

• inputting specification information about a pipeline process of an instruction to be executed by the processor, the specification information including time for the processor to access hardware resources for the instruction;
• inputting an instruction string in which a hazard is caused among a plurality of instructions when the processor executes the instruction;
• obtaining pipeline process information output when the pipeline control mechanism of the processor controls the instruction string in which the hazard was caused such that the hazard can be cleared;
• listing states in which new hazards are caused by executing a new instruction by the processor according to the pipeline process information and the specification information after execution of the instruction string in which the hazard was caused, the states including information on a series of instructions in time order that causes the new hazards;
• and
• generating an instruction string corresponding to each of the states listed by said listing step.

An automatic instruction string generating method for verifying operations of a pipeline control mechanism of a processor, comprising the steps of:

• inputting specification information about a pipeline process of an instruction to be executed by the processor;
• listing, according to the specification information, states in which hazards are caused among a plurality of instructions;
• generating an instruction string corresponding to each of the states listed by said listing step;
• adding before the instruction string an instruction to initialize an internal state of the processor into a state required to verify an operation of the pipeline control mechanism;
• and
• adding after the instruction string corresponding to each of the states listed by said listing step an instruction to store in specified storage means data required to verify the operation of the pipeline control mechanism.

An automatic instruction string generating method for verifying operations of a pipeline control mechanism of a processor, comprising the steps of:

• inputting specification information about a pipeline process of an instruction to be executed by the processor;
• listing, according to the specification information, states in which hazards are caused between a last started instruction and an instruction preceding the last started instruction by execution of the last started instruction after the pipeline process has processed a pipeline of the processor without a stop;
• generating an instruction string corresponding to each of the states listed by said listing step;
• adding before the instruction string an instruction to initialize an internal state of the processor into a state required to verify an operation of the pipeline control mechanism;
• and
• adding after the instruction string corresponding to each of the states listed by said listing step an instruction to store in specified storage means data required to verify the operation of the pipeline control mechanism.

An automatic instruction string generating method for verifying operations of a pipeline control mechanism of a processor, comprising the steps of:

• inputting specification information about a pipeline process of an instruction to be executed by the processor;
• inputting an instruction string in which a hazard is caused among a plurality of instructions when the processor executes the instruction;
• obtaining pipeline process information output when the pipeline control mechanism of the processor controls the instruction string in which the hazard was caused such that the hazard can be cleared;
• listing states in which new hazards are caused by executing a new instructions by the processor according to the pipeline process information and the specification information after execution of the instruction string in which the hazard was caused;
• generating an instruction string corresponding to each of the states listed by said listing step;
• adding before the instruction string an instruction to initialize an internal state of the processor into a state required to verify an operation of the pipeline control mechanism;
• and
• adding after the instruction string corresponding to each of the states listed by said listing step an instruction to store in specified storage means data required to verify the operation of the pipeline control mechanism.

An automatic instruction string generating device for verifying operations of a pipeline control mechanism of a processor, comprising:

• specification information storing means for inputting and storing specification information about a pipeline process of an instruction to be executed by the processor, the specification information including time for the processor to access hardware resources for the instruction;
• hazard state listing means for listing, according to the specification information stored in said specification information storing means, states in which hazards are caused among a plurality of instructions in time order;
• and
• instruction string generating means for generating an instruction string corresponding to each of the states listed by said hazard state listing means.

An automatic instruction string generating device for verifying operations of a pipeline control mechanism of a processor, comprising:

• specification information storing means for inputting and storing specification information about a pipeline process of an instruction to be executed by the processor, the specification information including time for the processor to access hardware resources for the instruction;
• hazard state listing means for listing, according to the specification information stored in said specification information storing means, states in which hazards are caused between a last started instruction and an instruction preceding the last started instruction by execution of the last started instruction after the pipeline process has processed a pipeline of the processor without a stop, the states including information on a series of instructions in time order that causes the hazards;
• and
• instruction string generating means for generating an instruction string corresponding to each of the states listed by said hazard state listing means.

An automatic instruction string generating device for verifying operations of a pipeline control mechanism of a processor;

• comprising:
• specification information storing means for inputting and storing specification information about a pipeline process of an instruction to be executed by the processor, the specification information including time for the processor for access hardware resources for the instruction;
• hazard generation instruction string input means for inputting an instruction string in which a hazard is caused among a plurality of instructions when the processor executes the instruction;
• instruction execution information obtaining means for obtaining pipeline process information output when the pipeline control mechanism of the processor controls the instruction string in which the hazard is caused and which is input by said hazard generation instruction string input means such that the hazard can be cleared;
• hazard state listing means for listing states in which new hazards are caused by executing a new instructions by the processor according to the pipeline process information and the specification information after execution of the instruction string in which the hazard was caused, the states including information on a series of instructions in time order that causes the hazard;
• and
• instruction string generating means for generating an instruction string corresponding to each of the states listed by said hazard state listing means.

An automatic instruction string generating device for verifying operations of a pipeline control mechanism of a processor, comprising:

• specification information storing means for inputting and storing specification information about a pipeline process of an instruction to be executed by the processor;
• hazard state listing means for listing, according to the specification information stored in said specification information storing means, states in which hazards are caused among a plurality of instructions;
• instruction string generating means for generating an instruction string corresponding to each of the states listed by said hazard state listing means;
• first instruction string adding means for adding before the instruction string generated by said instruction string generating means an instruction to initialize an internal state of the processor into a state required to verify an operation of the pipeline control mechanism;
• and
• second instruction string adding means for adding after the instruction string generated by said instruction string generating means an instruction to store in specified storage means data required to verify the operation of the pipeline control mechanism.

An automatic instruction string generating device for verifying operations of a pipeline control mechanism of a processor, comprising:

• specification information storing means for inputting and storing specification information about a pipeline process of an instruction to be executed by the processor;
• hazard state listing means for listing, according to the specification information stored in said specification information storing means, states in which hazards are caused between a last started instruction and an instruction preceding the last started instruction by execution of the last started instruction after the pipeline process has processed a pipeline of the processor without a stop;
• instruction string generating means for generating an instruction string corresponding to each of the states listed by said hazard state listing means;
• first instruction string adding means for adding before the instruction string generated by said instruction string generating means an instruction to initialize an internal state of the processor into a state required to verify an operation of the pipeline control mechanism;
• and
• second instruction string adding means for adding after the instruction string generated by said instruction string generating means an instruction to store in specified storage means data required to verify the operation of the pipeline control mechanism.

An automatic instruction string generating device for verifying operations of a pipeline control mechanism of a processor, comprising:

• specification information storing means for inputting and storing specification information about a pipeline process of an instruction to be executed by the processor;
• hazard generation instruction string input means for inputting an instruction string in which a hazard is caused among a plurality of instructions when the processor executes the instruction;
• instruction execution information obtaining means for obtaining pipeline process information output when the pipeline control mechanism of the processor controls the instruction string in which the hazard is caused and which is input by said hazard generation instruction string input means such that the hazard can be cleared;
• hazard state listing means for listing states in which new hazards are caused by executing a new instruction by the processor according to the pipeline process information and the specification information after execution of the instruction string in which the hazard was caused;
• instruction string generating means for generating an instruction string corresponding to each of the states listed by said hazard state listing means;
• first instruction string adding means for adding before the instruction string generated by said instruction string generating means an instruction to initialize an internal state of the processor into a state required to verify an operation of the pipeline control mechanism;
• and
• second instruction string adding means for adding after the instruction string generated by said instruction string generating means an instruction to store in specified storage means data required to verify the operation of the pipeline control mechanism.

A method to generate instruction strings that will cause hazards in a pipeline processor, comprising the steps of:

• inputting specification information on the pipeline processor, the specification information including time for the processor to access hardware resources for instructions processed by the processor;
• listing hazard states for the hazards achievable with the specification information, the hazard states including information on a series of instructions in time order that causes hazards;
• and,
• generating instruction strings corresponding to each hazard state.

A device to generate instruction strings that will cause hazards in a pipeline processor, comprising:

• a specification information storing device storing specification information on the pipeline processor, the specification information including time for the processor to access hardware resources for instructions processed by the processor;
• a hazard state listing device listing hazard states for the hazards achievable with the specification information, the hazard states including information on a series of instructions in time order that causes hazards;
• and
• an instruction string generating device generating instruction strings corresponding to each hazard state.