US 5,673,422 A · Semiconductor integrated circuit for processing image data

Abstract

A frame buffer memory includes a main memory of a DRAM, a cache memory of a SRAM, a first transfer bus for transferring data of 256 bits, for example, between the main memory and the cache memory, a pixel processing unit for carrying out a predetermined operational process according to data provided from the cache memory and externally applied data, a compare unit for comparing the data provided from the cache memory with externally applied data, a transfer bus for transferring data from the cache memory to the pixel processing unit and the compare unit, a transfer bus for transferring resultant data from the pixel processing unit to the cache memory, and a serial access memory for storing data read out from the main memory and providing the stored data serially to an outside world. According to the structure, an .alpha.-blend process, a raster operation, a Z compare process and the like required for graphics can be carried out at high speed with flexibility.

Claims40

Dependent claims

An image processing circuit comprising:

match compare means for comparing current depth data of a currently displayed screen with next depth data of a next screen to be displayed to make determination whether said current depth data matches said next depth data,
magnitude compare means for comparing said current depth data with said next depth data to make determination of the magnitude of said current depth data and said next depth data,
means for generating a control signal in response to results of said match compare means and said magnitude compare means,
match control means for controlling said match compare means so as to determine whether a predetermined bit in said current depth data matches a corresponding bit in said next depth data, and
magnitude control means for controlling said magnitude compare means so as to determined the magnitude between a bit in said current depth data other than said predetermined bit and a corresponding bit in said next depth data.

2 more elements

A semiconductor integrated circuit device comprising:

a semiconductor substrate,
a data input/output terminal for receiving externally applied image data,
first memory means formed at said semiconductor substrate for storing a plurality of image data,
second memory means formed at said semiconductor substrate for storing a plurality of image data, said second memory means having at least three ports for receiving and/or transferring image data,
first transfer means formed at said semiconductor substrate for transferring image data from/to said first memory means to/from a first port of said second memory means,
image processing means formed at said semiconductor substrate for carrying out a predetermined process according to first and second image data,
second transfer means formed at said semiconductor substrate for transferring said first image data from a second port of said second memory means to said image processing means,
third transfer means formed at said semiconductor substrate for transferring said second image data from said data input/output terminal to said image processing means, and
fourth transfer means formed at said semiconductor substrate for transferring resultant data from said image processing means to a third port of said second memory means, wherein
a larger amount of image data is transferable via said first transfer means than via said second and fourth transfer means.

7 more elements

A semiconductor integrated circuit device comprising:

a semiconductor substrate,
first memory means formed at said semiconductor substrate for storing a plurality of data,
second memory means formed at said semiconductor substrate for storing a plurality of first data, said second memory means having at least three ports for receiving and/or transferring image data,
a data input/output terminal for receiving an externally applied second data,
first transfer means formed at said semiconductor substrate for transferring data from/to said first memory means to/from a first port of said second memory means,
operation means formed at said semiconductor substrate for carrying out a predetermined operation according to the first and second data,
compare means formed at said semiconductor substrate for comparing said first data with said second data,
second transfer means formed at said semiconductor substrate for transferring said first data from a second port of said second memory means to said operation means and said compare means,
third transfer means formed at said semiconductor substrate for transferring said second data from said data input/output terminal to said operation means and said compare means,
fourth transfer means formed at said semiconductor substrate for transferring resultant data from said operation means to a third port of said second memory means,
a video output terminal,
a serial access memory formed at said semiconductor substrate for storing data read out from said first memory means and providing said stored data to said video output terminal serially,
a control signal input terminal for receiving an externally applied predetermined control signal,
a logic circuit responsive to the control signal from said control signal input terminal and resultant signal from said compare means for providing a write enable signal to said second memory means, and
a control signal output terminal for providing a resultant signal from said compare means, wherein
a larger amount of image data is transferable via said first transfer means than via said second and fourth transfer means.

13 more elements

An image storage processing system comprising:

a first semiconductor integrated circuit device including
a first semiconductor substrate,
a color data input/output terminal for receiving externally applied second color data,
first memory means formed at said first semiconductor substrate for storing a plurality of color data,
second memory means formed at said first semiconductor substrate for storing a plurality of first color data,
first transfer means formed at said first semiconductor substrate for transferring color data between said first and second memory means,
color data operation means formed at said first semiconductor substrate for carrying out a predetermined operation according to the first and second color data,
second transfer means formed at said first semiconductor substrate for transferring said first color data from said second memory means to said color data operation means,
third transfer means formed at said first semiconductor substrate for transferring said second color data from said color data input/output terminal to said color data operation means,
fourth transfer means formed at said first semiconductor substrate for transferring resultant data from said color data operation means to said second memory means,
a video output terminal,
a serial access memory formed at said first semiconductor substrate for storing data read out from said first memory means and providing said stored data serially to said video output terminal, and
a control signal input terminal for receiving an externally applied predetermined control signal,
wherein said second memory means has writing of resultant data transferred by said fourth transfer means enabled in response to the control signal from said control signal input terminal, and
a second semiconductor integrated circuit device including
a second semiconductor substrate,
a depth data input/output terminal for receiving externally applied depth data,
third memory means formed at said second semiconductor substrate for storing a plurality of depth data,
fourth memory means formed at said second semiconductor substrate for storing a plurality of depth data,
fifth transfer means formed at said second semiconductor substrate for transferring depth data between said third and fourth memory means,
depth data compare means formed at said second semiconductor substrate for comparing first depth data with second depth data,
sixth transfer means formed at said second semiconductor substrate for transferring said first depth data from said fourth memory means to said depth data compare means,
seventh transfer means formed at said second semiconductor substrate for transferring said second depth data from said depth data input/output terminal to said depth data compare means,
eighth transfer means formed at said second semiconductor substrate for transferring said second depth data to said fourth memory means, and
a control signal output terminal connected to said control signal input terminal of said first semiconductor integrated circuit device, and providing resultant data from said depth data compare means,
wherein said fourth memory means has writing of second depth data transferred by said eighth transfer means enabled in response to the resultant signal from said depth data compare means.

23 more elements

Dependencies are inferred from the claim text.

Semiconductor integrated circuit for processing image data

Life of this patent

Semiconductor integrated circuit for processing image data

Life of this patent

Abstract

Claims40