Memory request and control unit including a mechanism for issuing and removing requests for memory access

In an information processor having a CPU in communication with dynamic random access memory (DRAM), a memory request generation and control unit, comprising a memory request generator for issuing low and high priority requests for data to a dynamic random access memory (DRAM) controller sequencer for loading data from the DRAM into a first-in-first-out device (FIFO) for transfer to a display pipeline, said memory request generator comprising:

• determining means for determining a FIFO data level of the FIFO;
• first comparator means, responsive to said determining means, for comparing the FIFO data level against a predetermined low-priority threshold value;
• second comparator means, responsive to said determining means, for comparing the FIFO data level against a predetermined high-priority threshold value, the high-priority threshold value indicative of a potential FIFO underrun condition;
• counter means for counting the number of addresses that have been latched by said DRAM controller sequencer for sending to the DRAM and for providing an output whenever a predetermined number has been counted;
• first generator means, responsive to said first comparator means and said counter means, for issuing a low priority request for data when the FIFO data level falls below or is equal to the low-priority threshold value and for removing an issued low priority request for data when said counter means provides the output and the FIFO data level determined by said determining means is greater than the low-priority threshold value;
• and
• second generator means, responsive to said second comparator means and said counter means, for issuing a high priority request for data when the FIFO data level falls below or is equal to the high-priority threshold value and for removing an issued high threshold request for data when said counter means provides the output and the FIFO data level determined by said determining means is greater than the high-priority threshold value;
• wherein said DRAM controller sequencer is in communication with said memory request generator, the CPU, and DRAM for receiving and arbitrating among the first, second and a third request for data issued by the CPU according to a predetermined priority scheme.

A method for issuing prioritized requests comprising first and second requests for data for loading into a first-in-first-out device (FIFO) and arbitrating among the first, second and a third request for data issued by an information processor, comprising the steps of:

• determining a FIFO data level of the FIFO;
• comparing the FIFO data level against a predetermined first value;
• comparing the FIFO data level against a predetermined second value less than the first value, the second value representing a FIFO underrun threshold;
• counting the number of data elements to be loaded into the FIFO;
• providing a control output whenever a predetermined number of data elements to be loaded into the FIFO has been counted;
• issuing a first request for data when the FIFO data level falls below or is equal to the first value;
• removing an issued first request when the control output is provided and the FIFO data level is greater than the first value;
• issuing a second request for data when the FIFO data level falls below or is equal to the second value;
• removing an issued second request when the control output is provided and the FIFO data level is greater than the second value;
• and
• arbitrating among the first, second and a third request for data issued by the CPU according to a predetermined priority scheme.

A CPU-driven data processing apparatus, comprising:

• a memory;
• a controller sequencer in communication with said memory;
• a display first-in-first-out (FIFO) module in communication with said controller sequencer and comprising:
• a first-in-first-out device (FIFO),
• determining means for determining a FIFO data level of the FIFO,
• first comparator means, responsive to said determining means, for comparing the FIFO data level against a predetermined low-priority threshold value,
• second comparator means, responsive to said determining means, for comparing the FIFO data level against a predetermined high-priority threshold value, the high-priority threshold value indicative of a potential FIFO underrun condition,
• counter means for counting the number of addresses that have been latched by the controller sequencer for sending to said memory and for providing an output whenever a predetermined number has been counted,
• first generator means, responsive to said first comparator means and said counter means, for issuing a low priority request for data when the FIFO data level falls below or is equal to the low-priority threshold value and for removing an issued low priority request for data when said counter means provides the output and the FIFO data level determined by said determining means is greater than the low-priority threshold value, and
• second generator means, responsive to said second comparator means and said counter means, for issuing a high priority request for data when the FIFO data level falls below or is equal to the high-priority threshold value and for removing an issued high priority threshold request for data when said counter means provides the output and the FIFO data level determined by said determining means is greater than the high-priority threshold value;
• a display pipeline coupled to said display FIFO module;
• and
• a display device, coupled to said display pipeline, for outputting the data, wherein said controller sequencer receives and arbitrates among the first, second and a third request for data issued by a CPU according to a predetermined priority scheme.