High speed two-port interface unit where read commands suspend partially executed write commands

A storage interface unit which is comprised of:

• a primary I/O port that includes a clock line which carries a cyclic clock signal, a time-shared data bus, write command lines, and read command lines;
• a write input circuit which receives write commands from said write command lines and simultaneously receives accompanying write data words from said time-shared data bus, at a rate of one write command and one data word per clock cycle;
• several write execution modules which are serially intercoupled from said write input circuit to a time-shared memory and which execute said received write commands by passing each such command and accompanying write data word through said write execution modules in a pipelined fashion to said time-shared memory;
• a read input circuit which in a single clock cycle, receives a read command while said write commands are being executed;
• a control circuit having control lines coupled to said write input circuit and write execution modules and time-shared memory and read input circuit, which in response to the received read command
• a) temporarily suspends the execution of said received write commands after their passage through said execution modules has begun,
• b) read data from said time-shared memory in a first clock cycle immediately after said read command is received by bypassing said serially intercoupled write execution modules, and
• c) sends data from said memory on said time-shared data bus in a second clock cycle immediately after said first clock cycle;
• and
• a second I/O port that includes an interrupt input line for carrying an interrupt signal;
• and wherein said control circuit includes interrupt response logic which, while said interrupt signal is present, a) inhibits said write input circuit and read input circuit from receiving any commands, b) inhibits said serially intercoupled write execution modules from passing write commands to said time-shared memory, and c) enables said time-shared memory to be read and written from said secondary I/O port.