Snooping of I/O bus and invalidation of processor cache for memory data transfers between one I/O device and cacheable memory in another I/O device

For a computer system containing a central processing unit (CPU), a cache, a system memory and a hierarchy of at least two buses through which data is passed between said CPU and I/O devices connected to said computer system said hierarchy of buses including a system bus for conducting data transfers relative to said CPU, said cache, and said system memory, and an I/O bus for connecting to said I/O devices, said I/O bus supporting I/O and memory data transfers between said I/O devices and said CPU, cache and system memory, as well as memory data transfers between pairs of said I/O devices wherein one device of each respective pair controls said I/O bus as an alternate master and the other device of the same pair contains addressable memory locations including memory locations cacheable in said cache, a method of maintaining coherency between data stored in the cacheable memory locations in said I/O devices and data stored in said cache when the data stored in said cacheable locations is modified by one of said I/O devices having alternate master control over said I/O bus;

• said method comprising:
• identifying said cacheable memory locations in the I/O devices;
• monitoring memory data transfers on said I/O bus with reference to the identified cacheable memory locations to detect when the one I/O device controlling said I/O bus is writing data to a cacheable memory location in another of said I/O devices;
• determining, for each data transfer detected in said monitoring step, the address of the respective cacheable location to which data is being written;
• and
• for each address determined in said determining step, detecting when said system bus is available for communicating signals to said cache, and then writing an invalidation signal, containing the address determined in said determining step, onto said system bus.

A computer system comprising a CPU, a cache, a cache controller, and a system memory, said system containing a hierarchy of plural buses through which data is transferred between said cache and I/O devices connected to said system, said hierarchy of buses including a first bus coupled directly to said CPU and cache, a second bus coupled to said system memory and linked to said CPU and cache only through said first bus, and a third bus for connecting said system to said I/O devices, said third bus being subject to alternate master control by said I/O devices and supporting data transfers directly between pairs of said I/O devices that are not directly detectable at said first and second buses;

• said computer system further comprising:
• at least one I/O memory device containing cacheable memory locations for storing data that is transferrable to said cache via said third, second and first buses;
• snooping logic monitoring said third bus for detecting when data is being written by a first one of said I/O devices to a cacheable memory location in a second one of devices, and
• means, coupled between said snooping logic and said second bus, and responsive to detection by said snooping logic that data is being written by the first I/O device to a cacheable memory location in the second I/O device, for presenting an invalidation signal on said second bus indicating the address of the cacheable memory location to which data is being written by said first I/O device;
• said invalidation signal being conveyed to said cache controller, via said second and first buses, enabling said cache controller to maintain coherency between said cache the cacheable memory location in said second I/O device if said cache then contains data copied from the cacheable memory location in said second I/O device.

A computer system comprising a CPU, a cache, a cache controller, a system memory, a system memory controller, a direct memory access (DMA) controller, a bus interface unit, a first bus linking said CPU, cache controller and system memory controller, a second bus linking said system memory controller, DMA controller and bus interface unit, and a third bus connected to said bus interface unit for linking said system to I/O devices including devices containing addressable memory locations that are directly cacheable in said cache;

• said third bus supporting transfers of data directly between pairs of said I/O devices attached thereto, in which one device of the respective pair of devices operates as an alternate master of said third bus to control the respective data transfer in a manner that is effectively invisible to said first and second buses and said CPU, cache controller and system memory controller;
• said bus interface unit comprising:
• snooping logic operating invisibly to said system memory controller for monitoring said third bus to detect when data is being written by one I/O device to a directly cacheable memory location contained in another I/O device;
• and
• means responsive to detection by said snooping logic that data is being written by said one I/O device to a directly cacheable memory location in said another I/O device, for presenting a cache invalidation signal to said system memory controller on said second bus;
• said cache invalidation signal including address information indicating the address of a respective directly cacheable memory location in said another I/O device to which data is being written;
• said cache invalidation signal being conveyed to said system memory controller via said second bus and passed along to said cache controller via said first bus, to enable said cache controller to determine if said cache contains data derived from the directly cacheable memory location to which data is being written, and in that event to invalidate the cache location containing said derived data;
• said second bus being potentially inaccessible to said means for presenting said cache invalidation signal when data is written to said another I/O device;
• and said means for presenting said cache invalidation signal including at least one buffer register for storing address information to be included in said cache invalidation signal when said means for presenting is ready to present a respective cache invalidation signal but said second bus is inaccessible to receive said respective cache invalidation signal.

For a computer system containing a central processing unit (CPU), a cache and cache controller coupled to said CPU, system memory coupled to said CPU, and an I/O bus for connecting said CPU, cache controller and system memory with I/O devices, wherein said I/O devices include memory devices containing addressable memory locations cacheable in said cache, and said I/O bus supports memory data transfers between two of said I/O devices, apparatus for maintaining consistency between data stored in said cache and the cacheable memory locations in said I/O devices, said apparatus comprising:

• snoop logic coupled to said I/O bus for detecting when a memory data transfer is being performed on said I/O bus between two of said I/O devices, and data is being transferred relative to a cacheable memory address location in one of said two I/O devices;
• invalidation signalling means responsive to detection by said snoop logic that data is being transferred relative to a cacheable memory location in said one I/O device, in a memory data transfer between said two I/O devices, for directing an invalidation signal, indicating the address of the cacheable memory location in said one I/O devise to said cache controller;
• said invalidation signal enabling said cache controller to invalidate a location in said cache containing data derived from the cacheable memory location, if there is a location in said cache containing the derived data 22.