System for aligning varying width instructions in a computer

Abstract

The invention defines a new computer architecture that will simultaneously improve the efficiency of the instruction word, and the speed of program execution. Instruction word efficiency is important to maximizing the use of available program memory space. The architecture described features an instruction memory that is wider than the minimum instruction width and equal to the maximum instruction width. The architecture is comprised of three sections; instruction memory, instruction read shift register, and control logic. The instruction memory width is equal to the maximum instruction width M (bits); where M is a twos multiple of the minimum instruction width K (bits). Instructions of various sizes are loaded into program memory in discrete blocks of size K. Consequently some multi-byte (assuming K=8) instructions are broken up and therefore occupy a portion of two adjacent memory locations. The Instruction Read Shift Register is best described as a shift register of total width M*3-K bits, containing (M*3-K)/K discrete positions each of width K bits. The shift register design provides for the execution of a new instruction every CPU cycle by holding the next instruction upstream in the shift register. The control circuits oversee the addressing of the instruction memory, instruction decode, loading of the read shift register, and shift control. The control circuits must recognize branch instructions and generate instruction memory addresses accordingly. The invention described herein also provides for the use of attribute instructions. Attributes can be linked to any basic instruction; creating a new, composite instruction that is much more powerful than any single member of the basic instruction set. Attributes in this inventioon can specify word widths for ALU manipulation, ROM and RAM address ranges, post increment/decrement operations for indirect addressing, and ALU control without introducing extra read cycles to instruction lookup. Attribute instructions, used in conjunction with the basic instruction set, simplify the definition of the basic set, increase the total number of valid instructions, maximize the efficiency of instruction memory space allocation, and improve throughput.

Dependencies are inferred from the claim text.