Data processor having capability to perform both floating point operations and memory access in response to a single instruction

A data processor comprising:

• a floating point unit including
• a floating point multiplier;
• a floating point arithmetic logic unit having an input multiplexed to an output of said floating point multiplier;
• and
• a pipeline control circuit for said floating point multiplier and said floating point arithmetic logic unit with pipeline stages for unpack, operate and normalize;
• memory circuitry;
• a source of instructions, said source of instructions including at least one vector floating point instruction designating both a floating point operation and a memory access;
• at least one control register holding for storing a memory address;
• and
• an instruction register and instruction logic circuitry connected to said floating point multiplier, said floating point arithmetic logic unit, said pipeline control circuit, said source of instructions and said at least one control register and responsive to a single vector floating point instruction received from said source of instructions to operate said floating point unit to perform said floating point operation designated by said single received vector floating point instruction and to perform a memory access employing said memory address stored in a control register designated by said received vector floating point instruction and incrementing said address stored in said control register designated by said single received vector floating point instruction to address a next data word concurrently with said operation of said floating point unit.